CMOS Op-amp Research Articles

Enhancing the design of a two-stage CMOS operational amplifier utilising the Bat Algorithm

ABSTRACT The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.

Automatic generation of macromodels and design equations for application to Op Amp design

SummaryOperational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple‐stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well‐known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple‐stage Op Amps.

Analysis and Comparison of Two Stage and Single Stage Operational Amplifiers Using 0.18µm Technology

Operational amplifier exists in many numbers of configurations. The there are many types of the Operational amplifiers. These are: two stage, single stage, three stage and multistage amplifiers. Identifying the better op amp is important to get better application. The better op amp will be selected by considering the performance parameters (DC Gain, Slew Rate, Power Dissipation, etc.) of op amp. In project work a two stage cmos and single stage CMOS operational has been compared and contrasted based on values of their performance parameters by using 0.18µm CMOS technology and the same power supply (5V). Based on these values, By comparing the performance parameters single stage CMOS op amp is more stable and operate longer duration of time than two stage cmos op amp with small energy loss; while two stage op amp produces the output which is twice larger than single stage op amp, and also the noise in the output of two stage op amp is less than single stage op amp. So to get more output it is better to use two stage op amps. By results and reasons suitable choices for high gain and high performance applications are two stage topologies.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

A programmable gain and bandwidth amplifier based on tunable UGBW rail-to-rail CMOS op-amps suitable for different bio-medical signal detection systems

This work presents a bio-medical amplifier with programmable Gain and Bandwidth. The bandwidth of the proposed amplifier is controlled by tuning the unity-gain bandwidth (UGBW) of a rail-to-rail CMOS operational amplifier. The amplifier gain is controlled by changing the input capacitors keeping the bandwidth unchanged. The proposed bio-medical amplifier capable to accommodate different signals with a bandwidth ranging from 50 Hz up to 10 kHz to detect different bio-potential signals: EEG, ECG, EMG, PCG, and Aps, using fixed and small load capacitance. The proposed bio-medical amplifier consists of two stages each one designed with Tera ohm CMOS pseudo-resistors used in the amplifier feedback. The lower cutoff frequency of the bio-medical amplifier is tuned using two biasing currents in the CMOS pseudo-resistors, while two biasing voltages in the CMOS op-amps tune the higher cutoff frequency. The gain of the proposed bio-medical amplifier is ranging from 44.3 dB to 65.1 dB. High stability of the CMOS based op-amps (phase margin ≥60°) over the whole Gain and Bandwidth ranges is achieved. The overall power consumption of the bio-medical amplifier is less than 3.28 μW at the maximum gain settings of 65 dB and a maximum bandwidth of 10 k Hz. The total harmonic distortion of the proposed amplifier less than 1.21% for an input amplitude of 1 mVpk-pk over the entire bandwidth. The Input referred noise spectral density is 426 nV/Hz @1 kHz for the maximum bandwidth settings. The proposed bio-medical amplifier achieves an IIP3 value of 19.44 dBm for the amplifier gain of 54.9 dB. The simulation results show that the proposed bio-medical amplifier is robust against the PVT variations. LT-spice simulations using the standard 90 nm CMOS technology under 1 V supply voltage are performed to validate the theoretical results of the proposed amplifier.

Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications

An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth.

New method to design feedback amplifier employing two-stage CMOS op amp

A new method to design feedback amplifier employing two-stage CMOS op amp is proposed. It is shown that although the open-loop phase margin of around 65 degrees is suitable for op amp connected as unity-gain amplifier (100% feedback), such is not the case when amplifier’s feedback factor of is less than 100%. In the proposed design method, the open-loop phase margin requirement is replaced by closed-loop bandwidth and quality factor of feedback amplifier such that a better control of the responses of the amplifier is achieved. Comparison of simulation results of feedback amplifiers obtained from the traditional method and the proposed method is given. It is demonstrated that the inverting amplifier obtained from the proposed method consumes somewhat less power than the one obtained from the traditional design, which employs the op amp with 65 degrees phase margin, while having comparable gain, bandwidth, transient and noise performances.

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node

This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60°. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.

Carbon Nanotube CMOS Analog Circuitry

Carbon nanotube (CNT) field-effect transistors (CNFETs) promise significant energy efficiency benefits versus today's silicon-based FETs. Yet despite this promise, complementary (CMOS) CNFET analog circuitry has never been experimentally demonstrated. Here we show the first reported demonstration of full CNFET CMOS analog circuits. For characterization, we fabricate analog building block circuits: multiple instances of two-stage op-amps. These CNFET CMOS op-amps achieve gain >700 (maximum derivative of output voltage with respect to differential input voltage), operate at a scaled sub-500 mV supply voltage, achieve high linearity (even when operating at these scaled voltages), and are robust over time (minimal drift over >10 000 cycled measurements over 12 h). Additionally, we demonstrate a front-end analog subsystem that integrates a CNFET-based breath sensor with an analog sensor interface circuit (transimpedance amplifier followed by a voltage follower to convert resistance change of the chemoresistive CNFET sensor into a buffered output voltage). These experimental demonstrations are the first reports of the CNFET CMOS analog functionality that is essential for a future CNT CMOS technology.

Offset voltage minimization based circuit sizing of CMOS operational amplifier using whale optimization algorithm

Evolutionary algorithms are simple and efficient techniques for optimization of VLSI circuits. In this work, Whale Optimization Algorithm (WOA) is used to design a two stage CMOS operational amplifier (OpAmp)with optimum area so as to achieve minimum offset voltage and also meet different design specifications such as Slew Rate, Gain etc. for the operational amplifier. For maintaining current imbalance at the output stage of the OpAmp, offset minimization is an important requirement. Algorithmic results were further validated by redesigning the OpAmp in the standard CADENCE Virtuoso circuit simulator. There is a good agreement found between the virtuoso simulated and algorithmic results. The results obtained from WOA is then compared with the performance of other algorithms such as Particle Swarm Optimization(PSO), Human Behaviour based Particle Swarm Optimization (HBPSO), Differential Evolution (DE) etc. Based on comparative analysis, it is found that the WOA performed better for circuit sizing the CMOS OpAmp for minimum offset as compared to the other algorithms by having a better convergence rate, low power dissipation and a minimum offset, although to achieve this, it required a little higher area.

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency.

An Optimized Device Sizing of Two-Stage CMOS OP-AMP Using Multi-Objective Genetic Algorithm

An Optimized Device Sizing of Two-Stage CMOS OP-AMP Using Multi-Objective Genetic Algorithm

Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback

This paper presents an ultra high gain two stage CMOS Operational Amplifier which is designed using self-cascoding and positive feedback technique in order to provide gain enhancement. By comparing the circuit with other designed circuits it has been shown that applying positive feedback increases the gain of the Op-Amp without affecting other properties of the amplifier. The proposed circuit is designed in 45 nm technology using Cadence Virtuoso Analog Design Environment tool at ±1 V supply. The Op-Amp is designed to achieve a high gain of 141 dB while maintaining a UGB of 101 MHz and phase margin of 60°. The simulation results conforms the estimated theoretical improvements. The dependence of various properties such as slew rate, UGB, settling time and phase margin of the designed Op-Amp on compensating capacitor CC has also been analyzed in this paper. Finally, the simulation results have been compared with a previously reported Op-Amp utilizing positive feedback technique.

Design and Analysis of High Gain, Low Power and Low Voltage a-Si TFT based Operational Amplifier

This paper investigates on the design of two stage Operational Amplifier (Op-Amp) with NMOS input at differential stage. This low power Op-Amp designed with Amorphous Silicon Thin Film Transistor (a-Si TFT) and MOS transistor. It is observed that the newly designed TFT Op-AMP operates in low voltage at 3V DC, with high gain, high output impedance and high phase margin and moderate power dissipation. A detailed design procedure is carried-out to design the proposed Op-Amp. HSPICE Circuit Simulator is used for simulation. Obtained results are compared with CMOS Op-Amp which uses the same circuit and design procedure. The output behavior of TFT Op-Amp is also compared with the existing work showing good agreement.

Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique

Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique

Design of Low Voltage Low Power OP-AMP using DTMOS Technique

ABSTRACT This paper demonstrates the design of low voltage, low power CMOS op-amp using DTMOS technique for low-power applications. The design goal is to achieve high gain, phase margin and minimum power dissipation at lower supply voltage. DTMOS transistor is proposed in this paper for the design of op-amp which replaces the normal CMOS transistors for designing a low power, low voltage two stage op-amp. A dc gain of 96.38 dB, a phase margin of 71.46o by achieving a unity gain bandwidth of 4.077 MHz while operating at 1V supply voltage. The performed simulation results show a power dissipation of 12.19 µW is achieved under 5 pF load in this design. The design and analysis is performed using 180 nm CMOS technology in Cadence Virtuoso ADE . Keywords Low power applications, Diff-amp, op-amp, DTMOS, Low power, Low voltage . 1. INTRODUCTION From the past few years due to the extensive growth of market for portable devices such as cell phones, portable computers, other low power applications and also the design of analog circuits which requires low power, low voltage with high performance has become an important issue now a day’s [2]. One of the limitations for implementation of portable devices and design of other low power circuits at low voltage is the threshold voltage (V

An Automation Methodology for Modeling Posynomial Equations for Use in CMOS OpAmp Synthesis

In this paper, we propose a novel methodology to automate the transistor-level sizing of OpAmps. Given the netlist and the specifications of the OpAmp, our methodology automatically produces a set of monomial design equations that can be solved using a geometric programming. The use of monomial models eliminates the overhead of generating elaborate posynomial design equations. This approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The results of a two stage OpAmp designed in TSMC 0.25μ technology prove the efficacy of our approach.

Design of 0. 13um CMOS Low Voltage Rail to Rail Fully Differential Operational Amplifier Review

An operational amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage and low power operational amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense. One of the most important features in low voltage amplifier designs is ensuring that the amplifier maintains constant behavior in the presence of rail-to-rail input common mode variations while providing a rail-to-rail output to maximize signal-to-noise ratio. As the supply voltage to a standard CMOS op-amp is reduced, the input common mode range and the output swing get reduced drastically. Special circuits have to be used to raise them up to rail-to-rail supply voltage. In this work we propose a design of a low-voltage CMOS rail-to-rail folded cascode operational amplifier to be realized in a standard 130 nm CMOS technology with 1.2V supply voltage and consumes power less than 400uW. A two stage miller compensated folded cascode op-amp has a UGB >10MHz and achieves a gain >80dB over almost full range of the common mode input voltage.