CMOS LSI Research Articles

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μm standard CMOS technology. The ZLT was irradiated with 60Co γ-rays up to 10 Mrad, and its I–V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of the CMOS LSI circuit by just replacing SLTs with ZLTs.

Event-Driven Tactile Sensing System Including 100 CMOS-MEMS Integrated 3-Axis Force Sensors Based on Asynchronous Serial Bus Communication

This paper describes an event-driven tactile sensing system including 100 CMOS-MEMS integrated 3-axis force sensors of 2.7 mm square footprint for providing robot tactile sensation. The system has the following features: (1) the event-driven function of the CMOS LSI integrated in the sensor can reduce the number of stimulated sensors, (2) the stimulated sensors send data packets on a shared differential bus line of 90 cm by asynchronous serial communication, and (3) the data collision avoidance and adaptation functions of the sensor enable multiple sensors to be stimulated simultaneously. According to the event-driven function, the sensor sends data packets only when the digital sensing value is over a set threshold. The collision avoidance function detects data collisions, stops sending data, and avoids further collisions. The adaptation function varies the time interval between data packets and reduces the bus occupation by a specific sensor. These functions make the sensor autonomous to some extent that can judge whether and when to send data packets. The sensor in the system can operate at a data sending rate of 1 Mbps, 2 Mbps, 4 Mbps, or 8 Mbps by configurations. When 100 sensors with the same function settings are stimulated, almost the same amount of data packets are received from each sensor. As the data rate changing from 1 Mbps to 8 Mbps, the average sampling frequency of the 100 sensors is about 36.87 Hz, 73.00 Hz, 142.99 Hz, and 274.28 Hz with the data packet format of 244 bits.

High-Voltage LDMOS Transistors on an SOI Structure for Electronics That Operate in Extreme Conditions

The parameters of high-voltage LDMOS transistors on a silicon structure on an insulator formed in a technological cycle combined with the manufacturing technology of low-voltage CMOS LSI are investigated. LDMOS transistors are studied under conditions of the temperature changing in the range –60 to 300°C and exposure to ionizing radiation.

2.4\xa0GHz wake-up receiver with suppressed substrate noise coupling

The switching noise generated in digital circuits propagates through conductive silicon substrate to analog circuits in a mixed-signal CMOS LSI. Substrate noise coupling may degrade the performance of the analog circuits, and may result in a fault operation of the mixed-signal LSI in the worst-case. In this paper, the substrate noise coupling between the clock recovery circuit and the input port of the envelop detector in a low-power wake-up receiver (WuRx) was investigated experimentally. The propagation path of the substrate noise coupling was clarified by comparing the experimental results with the circuit simulations on the basis of an equivalent circuit model. The design of the WuRx was modified on the basis of the findings to suppress the substrate noise coupling. The fabricated WuRx successfully operated a 100-kbps PWM signal with a carrier frequency of 2.4 GHz, and the effectiveness of the noise coupling suppression recipe was confirmed.

A Review on Increasing of Breakdown Voltage of Standard CMOS LSI Circuits by MEMS Post-Process

A Review on Increasing of Breakdown Voltage of Standard CMOS LSI Circuits by MEMS Post-Process

(Invited) Electrochemical Biosensors Based on CMOS LSI Chips

We have been working on electrochemical biosensing using CMOS chip as a platform. Three major electrochemical methods, amperometric (voltammetric), potentiometric, and impedance methods, are aimed to be done by electrodes on a CMOS chip. In amperometric measurement, carbon-ink is used to form electrochemically-stable electrodes instead of expensive gold electrode formation by photolithography. Enzymes and mediator (redox) molecules are immobilized in pieces of chromatography paper, and layers of such paper are placed directly on CMOS chip. Both amperometric and potentiometric detection of glucose concentration have been demonstrated. We have also been working on computer simulation and modeling of the three electrochemical measurements done by microscale electrodes on CMOS chip. Examples include 3D amperometric current simulation of 2D microelectrode array on a CMOS chip, potentiometric measurement of pH and DNA on an ion-sensitive field-effect transistor, as well as living cell monitoring based on impedance method. We also design CMOS integrated circuits for on-chip biosensing based on the electrochemical methods.

Integrated 0–30 V switching driver circuit fabricated by mesa isolation postprocess of standard 5 V CMOS LSI for MEMS actuator applications

A 30 V switching circuit with standard CMOS foundry-made transistors on a silicon-on-insulator (SOI) wafer is proposed.The key fabrication process is mesa isolation postprocessing that physically separates a series-connected transistor's body so that we can apply independent substrate (body) voltages to each transistor. The process is a combination of anisotropic and isotropic deep reactive ion etching (DRIE) with a single mask. In the experiment, CMOS transistors were fabricated on a 9-µm-thick 6-in. SOI wafer in an LSI foundry company, and the postprocess was carried out in a MEMS cleanroom. In this paper, full integration with gate-voltage-level shift circuits and dynamic driving of an electrostatic comb-drive MEMS device with series-connected transistors are presented.

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC's is presented. It is realized at three levels: CMOS devices --- typical analog or digital circuit fragments --- complete IC's. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI's are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10---20% for all types of radiation.

(Keynote) Heterogeneous Integration of MEMS by Adhesive Bonding

Technology called microsystems or MEMS (micro electro mechanical systems) has been developed and applied as value added devices for systems. It is based on semiconductor microfabrication integrating not only circuits but also sensors, actuators and microstructures. MEMS as switches and filters fabricated on CMOS LSI are needed for future multi-band wireless systems, in which good mechanical properties or piezoelectric materials are required for the MEMS and state of the art for the LSI. Such heterogeneous integration can be performed by transferring MEMS devices fabricated on a carrier wafer to a LSI wafer by adhesive bonding (Figure). Wafer level selective transfer from one carrier wafer to multiple target wafers are needed for cost-effective integration of different size chips. The selective transfer technology was applied to multiple SAW (surface acoustic wave) resonators on LSI and tunable SAW filter having variable ferroelectric capacitor. Distributed tactile sensors are needed on the skin of robots to ensure their safety in nursing care robots. A tactile sensor network acquires sensing data from each tactile sensor element by autonomous data transmission (event driven). Capacitive tactile force sensors were formed on a communication LSI by adhesive bonding. An electron emitter array integrated with a 100×100 active-matrix driving LSI has been developed using the adhesive bonding. Massive parallel EB (electron beam) exposure systems for maskless lithography (digital fabrication of LSI) are under development. A nc (nanocrystalline)-Si emitter consists of cascaded tunnel junctions can be controlled at low voltage (10V). Resist patterning by the emitted electron was successfully confirmed. Amperometric biosensor in which 20×20 boron doped diamond electrode array are formed on LSI using the adhesive bonding. Distribution of chemicals like neurotransmitter can be detected owing to a wide potential window of the diamond electrode. Cost effective development is required for micro systems because they are versatile and not standardized. A hands-on access fabrication facility in our University is reuse of a production line for power transistor and donated equipments. Companies can easily access and utilize for their prototyping or small-volume production. It is equipped with 4 and 6 inch facilities. The users are charged depending on their amount of usage. They can access a lot of technology and know-how accumulated and can be assisted by skilled engineers. More than 150 companies are using this facility and it is allowed to sell produced small volume devices. Figure 1

Evaluation of sensitivity parameters for single event latchup effect in CMOS LSI ICs by pulsed laser backside irradiation tests

The results of computation-experimental modeling of single-event latchup effects under the laser radiation focused on the IC crystal backside—the substrate side—are presented. Possibilities of applying the technique of local laser irradiation to evaluate equivalent linear energy transfer of heavy ions in the case of the laser irradiation from the substrate side of IC crystal are analyzed. The experimental results obtained using the pulsed laser installation and accelerators of charged particles for a series of modern LSI ICs are compared.

Temperature Distribution Analysis of CMOS LSI With On-Chip Sensing Device Arrays

A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip have been measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode or n-MOSFET array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor are analyzed as well as transient phenomena. Temperature $T$ decreases with the distance $L$ , is proportional to the reciprocal of $L~(1/L)$ , and empirical equations have been proposed. The results of both p-n diode and n-MOSFET sensors are nearly the same. A thermal simulation gives an $L$ dependence of $T$ similar to the measured result. $T$ of 160 pin QFP becomes lower than that of 80 pin due to its larger outline, but $L$ dependence of $T$ is similar. The abrupt and gradual change of $T$ at the heater switching suggests both fast and slow processes in thermal conduction. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways.

Integrated CMOS-MEMS Technology and Its Applications

Fusion of microelectromechanical systems (MEMS) with CMOS LSI technologies is a promising way to develop high functional devices. We have been developing the integrated CMOS-MEMS technology that fabricates MEMS devices on CMOS LSI[1-2]. Thetechnology has the features ofhigh-functionality, high-accuracy, and mass-production.In this paper, first, MEMS technology trends and the concept of the integrated CMOS-MEMS technology are described. Next, we present the multi-physics simulation for the CMOS-MEMS technology[3-4]. Finally, as the examples, we demonstrate the arrayed CMOS-MEMS accelerometer[5-7].Prospects and challenges of the integrated CMOS-MEMS technology are described from the view point of CMOS-LSI (Fig.1). It indicates that this technology gives the solution of developing high functional devices.We have developed the multi-physics simulation platform to analyze the electromechanical behaviors of MEMS and CMOS simultaneously. Based on the analytical model, the equivalent circuit was proposed to simulate the above behavior on a Verilog-A compatible hardware description language (Fig.2).Small size and wide range accelerometers are increasingly in demand in the various system. Figure 3 shows the proposed arrayed CMOS-MEMS accelerometer that was capable of detecting a wide range of acceleration. The MEMS accelerometer was fabricated by gold electroplating with post-CMOS process. We can obtain the 3-by-3 arrayed MEMS accelerometer with the sensing range from 1.7G to 20G(Fig. 4). Also, using the simulation results obtained by the above multi-physics platform, we can realize the CMOS-MEMS accelerometer.In conclusion, it is confirmed that the integrated CMOS-MEMS technology will pave the way for the More than Moore technology.

Si Interposers with 15-^|^mu;m-thick Spiral Inductors and SrTiO3 Thin Film Capacitors for Novel 3D Stacked Buck Converters

We have developed a Si interposer with multilayer 15-μm-thick Cu wiring and SrTiO3 (STO) thin film capacitors to help create novel 3D stacked buck converters, which consist of a CMOS LSI that includes active components and a Si interposer with an LC output filter. A spiral inductor made using 15- μm-thick Cu wiring was stacked over an STO thin film capacitor in the Si interposer without any deterioration in capacitance and leakage current. A minimum line/space of 20 μm/20 μm and a minimum via-hole diameter of 30 μm were achieved to create 15-μm-thick Cu wiring patterns in the Si interposer. A newly developed chemically-amplified positive-tone resin was used as the interlayer dielectrics in the Si interposers to avoid under-exposure at the bottom of thick photo-sensitive resin and to obtain fine-pitch wiring patterns. The power efficiency of buck converters depends on the parasitic resistance of the embedded inductors. As a result, the 15-μm-thick inductor enhances the efficiency of an output current of 100 mA by 12% as compared to a 5- μm-thick inductor. The developed Si interposer with 15-μm-thick wiring layers will contribute to creating a 3D stacked buck converter for low-power and high-performance 3D integrated systems.

Integration of Series-Connected On-Chip Solar Battery in a Triple-Well CMOS LSI

A method of constructing a series-connected on-chip solar battery for integration into system LSIs using a triple-well CMOS process is presented. The triple-well CMOS process has various advantages, i.e., CMOS circuits are independent of the substrate voltages integrating series-connected on-chip solar batteries and have no leakage problems. The advantages of this method have been proved by ring oscillator operations with a solar battery voltage of 1.3 V, which is higher than those of single and conventional series-connected solar batteries. The current versus area optimization for series-connected solar batteries is considered.

CMOS LSI for Brain-machine Interface Used in Bidirectional Communication

CMOS LSI for Brain-machine Interface Used in Bidirectional Communication

Multi-band radio-frequency filters fabricated using polyimide-based membrane transfer bonding technology

In this paper, we present a polyimide-based Si membrane transfer bonding technology and its application to CMOS-compatible integration of different modes of AlN/Si composite piezoelectric MEMS resonators. The thermosetting polyimide, which has excellent chemical resistance and thermal stability, is used as a bonding adhesion, and is successfully removed as a sacrificial layer by O2 plasma to release free-standing MEMS devices. The whole process temperature is below 350 °C and compatible with CMOS LSI. Using this technology, different modes of AlN/Si resonators, which are film bulk acoustic wave resonators and wine-glass mode disk-type resonators, have been co-fabricated on the same wafer. We also fabricated a ladder-type FBAR filter with a center frequency of 7.71 GHz and a mechanically coupled disk-array filter with a center frequency of 292.8 GHz.

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40GHz for an automatically routed 4 × 4 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

MNM-3B-2 WSiとLSI配線工程互換プロセスを用いたモノリシック集積化MEMS圧カセンサ(セッション 3B 情報・精密機器におけるマイクロ・ナノテクノロジー2)

We have developed back-end-of-line (BEOL) MEMS processes for monolithically integrating MEMS and CMOS-LSI. The processes do not affect the performance of the LSI because only conventional materials for CMOS LSI are used and all process temperatures are less than 450 degree C. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm^2 using the BEOL MEMS processes. Multi-sensor chip with a size of 1.7 by 1.9 mm^2 which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated.

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.

Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490MHz and a supply voltage (VDD) of 0.75V was 104.1µW, i.e., 21.6% that (482.3µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51nW, which was only 1.69% that (1, 153nW) of the conventional SR circuit.