CMOS Low-dropout Regulator Research Articles

Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator

An easy-to-use efficient auto-design approach to achieve a synchronous optimization and solution for multiple performance objectives of a CMOS low-dropout regulator (LDO) circuit is proposed. As a core algorithm, response surface methodology (RSM) is adopted to automatically implement the design parameter modeling and solving of the LDO. The precision response surface models for the temperature coefficient (TC) and power supply rejection ratio (PSRR) are established efficiently based on only 27 sets of Cadence sampling datasets, by which the optimal performance solution with a superior tradeoff on TC and PSRR can be obtained. Along with a complete auto-design flow, the pre/post-layout simulations of the LDO circuit by SMIC 180 nm/3.3 V CMOS technology are performed, it can be observed that the auto-improved LDO has a significant better 35.20 ppm/°C TC feature compared with 48.46 ppm/°C that recorded by the manual design. Synchronously, the PSRR is improved from −59.497 Hz@DC to −92.89 Hz@DC with a great increase ratio by 56 % up.

A Low-quiescent Current Full on-chip 1.2 V CMOS Low Drop-Out Regulator

This paper presents a fully-integrated low-power 0.18 µm CMOS Low-Dropout (LDO) regulator for battery operated portable devices. It provides an accurate 1.2 V output voltage from 3.3 V to 1.3 V input voltages up with only 5.9 µA quiescent current, including an all-MOS 0.4 V reference voltage.

A programmable multi-output technique in LDO regulator for multi-reference SAR ADC application

ABSTRACTA multi-output and high-precision output-tuning technique in a low-dropout regulator (LDO) for multi-reference low-power SAR ADC is proposed in this article. A programmable resistor string is utilised for multi-output, and a tuneable resistor ladder is introduced in the feedback network for high-precision LDO output control. The applicability and superiority of this proposed approach are verified by the design of a 65 nm CMOS LDO with programmable output. The design results show that the LDO output ranges from 0.4 to 1.2 V with 0.2 V/step, and the output voltage can be precisely tuned by 0.05 V/step within a range of 0.8–1.15 V. The line regulation of this LDO is about 0.27 mV/V. The multi-output ability enables the LDO to drive five light loads simultaneously, and the high-precision tuning ability can effectively overcome the output errors caused by power supply variation, temperature drift and other non-ideal factors.

Effect of R-C Compensation on Switching Regulation of CMOS Low Dropout Regulator

Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100^o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

A Fully-Integrated CMOS LDO Regulator for Battery-Operated On-Chip Measurement Systems

This paper presents a fully-integrated 0.18 μm CMOS low drop-out (LDO) regulator designed to drive on-chip low power front-end sensor nodes. The proposed LDO is based on a simple telescopic amplifier stage with internal cascode compensation driving a PMOS pass-device, providing a high precision 1.8 V output voltage for input voltages from 3.6 V to 1.92 V up to a 50 mA load current with only 22 μA quiescent current. Line and load regulation are respectively better than 0.017 mV/V and 0.003 mV/mA, while recovery times are below 4 μs over a (-40 °C, 120 °C) temperature span.

PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.

CAPACITOR-LESS LOW-DROPOUT VOLTAGE REGULATOR

A 1.2-V 40-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitorfree operation. The proposed LDO has been implemented in a tsmc65nm CMOS technology, and the total error of the output voltage due to line and load variations is less. Moreover, the output voltage can recover with ≈2.3μs for full load current changes. The power-supply rejection ratio at 1 MHz is 26 dB.

A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast transient response

This paper presents a low-dropout regulator (LDO) for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59° phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6-μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113 μA. The line regulation and load regulation are improved to 0.1 mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90nm CMOS process is only 0.054mm2. Experimental results show that the developed LDO can supply up to 15mA and it presents a very fast transient response, with a settling time of approximately 30ns and a voltage drop of 200mV when the load current changes from 100nA to 9mA.

An Ultra-Low Quiescent Current CMOS Low-Dropout Regulator with Small Output Voltage Variations

An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm2. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.

Fast transient current-steering CMOS LDO regulator based on current feedback amplifier

This paper presents a current-steering approach to implement a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) topology. The circuit does not require any internal compensation capacitor, being stable for a wide range of output load currents [0–100mA] and a 1μF output capacitor. The CFA consists of an open-loop voltage follower with output local current–current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. Post-layout simulation results for a 0.35μm CMOS process design reveal that the proposed LDO requires 59μA quiescent current at no-load condition and at full-load condition has a current efficiency of 99.8%. For a 1μF output capacitor, the maximum output voltage variation to a 0–100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than −56dB over the entire load current range.

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7 pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200 × 280 µm2. The simulation results under mixed-signal 0.18 µm 1P6M process show that this novel LDO's output voltage can recover within 1.7 µs (rising) and 2.41 µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5 V for a load current 50 mA and an output voltage of 1.8 V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100 pF. Moreover, it can achieve a PSR of −78.5 and −73 dB at 1 and 10 kHz, respectively.

Design of Monolithic CMOS LDO Regulator With ${\rm D} ^{2}$ Coupling and Adaptive Transmission Control for Adaptive Wireless Powered Bio-Implants

This paper presents a monolithic CMOS low drop-out regulator for adaptive wireless powered bio-implants. A dual-loop control scheme is proposed to enhance load/DVS transient response, without a filter capacitor. The inner loop employs a direct dynamic coupling technique to improve transient response by directly detecting voltage variations through a capacitive coupling high-pass filter. Meanwhile, the outer loop adopts an adaptive transmission control to improve the regulator's large-signal transient response. The regulator is intrinsically stabilized without frequency compensation. Both small-signal and large-signal analysis are provided as design guidelines. The proposed regulator was fabricated with a 0.35-μm CMOS process, with an active die area of 0.35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Experimental results demonstrate a 1.6-μs/V down-tracking and 2.2- μs/V up-tracking speed for DVS reference tracking, with undershoot/overshoot voltages controlled below 90 mV. Without a filter capacitor, the output voltage of the regulator recovers within 2.0 μs for 100-mA load change, with less than 90-mV variation. The current/power efficiency stays above 93/78% over the entire interested load current range, with a peak value of 99.96/91.1%, respectively.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer

An energy-efficient voltage buffer for a low-dropout regulator (LDO) is presented in this paper. The voltage buffer contains a current-boosting circuit with quick-on and auto-off features so that it can momentarily provide an extra current to charge and discharge the large gate capacitance of the power transistor. The voltage buffer is therefore able to increase the slew rate at the gate of the power transistor, whereas the quiescent current of the LDO remains constantly low in the steady state. Moreover, the proposed current-boosting circuit has a capacitive shunt feedback network to improve the loop bandwidth of the LDO. The proposed voltage buffer is applied to an LDO implemented in a 0.35-μm CMOS technology. The LDO operates at a 2-V supply, and the regulated voltage is 1.8 V. The maximum output current is 100 mA. The measured quiescent current is about 4 μA. The load transient deviation of the regulated voltage is small. The proposed voltage buffer can effectively reduce the transient voltage spikes.

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout (LDO) regulator for system-on-chip (SoC) applications is presented. By adopting AC-boosting and active-feedback frequency compensation (ACB-AFFC), the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement

An active-frequency compensation circuit for low- dropout regulators (LDOs) is presented. Compared with the conventional compensation scheme, the proposed circuit can greatly boost the effective current multiplication factor by at least one order of magnitude without increasing any power consumption. Hence, the proposed circuit can generate an internal lower frequency zero and push parasitic poles toward extremely high frequency such that the loop bandwidth can be extended drastically. The required on-chip capacitance is reduced to 0.4 pF, comparing to 5 pF in the conventional compensation scheme. The slew rate at the gate drive of the LDO is also improved by the proposed error amplifier. Implemented in a 0.35 mum 2P4M CMOS process, the LDO with the proposed active-frequency compensation circuit consumes 27 muA ground current at 150-mA maximum output current with a dropout voltage of 200 mV. Experimental results show that the proposed LDO structure has achieved only 10% settling time of the conventional compensation scheme.

A CMOS Low Dropout Regulator with Extended Stable Region for the Effective Series Resistance of the Output Capacitor

In this paper, a new compensation scheme and a corre-sponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5V/150mA LDO has been implemented using a 0.5-μm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33μF and no ESR.