A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

Abstract

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7 pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200 × 280 µm2. The simulation results under mixed-signal 0.18 µm 1P6M process show that this novel LDO's output voltage can recover within 1.7 µs (rising) and 2.41 µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5 V for a load current 50 mA and an output voltage of 1.8 V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100 pF. Moreover, it can achieve a PSR of −78.5 and −73 dB at 1 and 10 kHz, respectively.