Abstract
Recent developments in system-on-chip (SoC) applications lead to an increasing attention on biomedical implantable IC designs. Being implantable, a CMOS low dropout regulator (LDR) with high power supply rejection (PSR) must have an on-chip output capacitor. To achieve a high PSR over a wide frequency range, a cascode technique with power NMOS and power PMOS is utilized to increase the output impedance of the LDR so that the output voltage can be less susceptible to any changes in the input voltage. With this technique, a clean and stable voltage can be produced. The test chip is implemented by TSMC 0.18um 1P6M CMOS technology with an area of 0.872×0.561 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured PSR at full load without using large external output capacitor is -33.6 dB at 60MHz and the ripple is 28mV. The power consumption is 2.13 mW and the efficiency is 77%.
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