CMOS Full Adder Research Articles

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.

VLSI Implementation of CMOS Full Adders with Low Leakage Power

VLSI Implementation of CMOS Full Adders with Low Leakage Power

Low power low voltage CMOS full adder cells based on energy-efficient architecture

This paper presents two low power full adder cells based on energy-efficient internal logic approach and pass transistor logic. These two new designs successfully operate at low voltage with tremendous signal integrity and driving capability. These designs are tested on a common environment using 90-nm CMOS process technology at many supply voltages. The adder cells are compared with eight of the popularly known full adders based on power consumption, speed and power-delay-product (PDP) and area efficiency. Intensive simulation runs on cadence environment and spectra shows that proposed full adder cells outperform their counterparts exhibiting 59.48% and 55.41% improvement in their PDP metrics.

MGDI based parallel adder for low power applications

The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two transistors by using this method. GDI technique allows for reduced power consumption, lower delay, lesser transistor count and decreased area of circuits. It also makes the system design less complex. Full adders and parallel adders, are major building blocks of different digital components like ALUs, DSPs etc. Hence, reducing power consumption of adders is very important. This work aims at building a parallel adder that consumes less power. A GDI based XOR gate is designed using which, a 10T full adder is designed which involves lesser number of devices compared to CMOS Full adder. The threshold loss in full adder is a major pitfall. A standard CMOS process compatible version of GDI cell, modified GDI, mGDI cell is proposed, using which a full adder is built. A 4-bit parallel adder is designed. The proposed technique consumes lesser area and has low power dissipation compared to CMOS design. Power consumption is reduced by 15% compared to CMOS design. Cadence tool at 180 nm is used to implement the designs.

Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc

Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc

Optimized CMOS Design of Full Adder using 45nm Technology

This paper presents low power full adder designed with pass transistor logic which reduces the area , power and delay. we compared conventional 28T CMOS full adder with 16T and 8T full adder in terms of area , power and delay using 45um Technology The schematic of all three design has been developed and its layout has been created using micro-wind tool. The result show that 8T full adder consumes 98% less power as conventional 28T& 65% less power compared to 16T full adder. Keywords Full adder, Pass Transistor logic(PTL), Transmission gate (TG) ,CMOS, Drive current, Channel Length.

Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder

In recent times, there is huge demand of low energy and low voltage in electronics industry. This low power dissipation is very useful in wireless operated devices and in consumer electronics market or battery operated devices. These low power circuits have ability to reduce the battery cells and reduction in these cells can enhance the uses of low weight and tiny size systems. Authors have designed the combinational circuit full adder using adiabatic method ECRL and also done comparison with traditional CMOS in this paper. The energy recovery logic ECRL is reversible logic and it can minimize the power up to 70-75.Authors have also done number of analysis on adiabatic methodology like altering the frequency and rise time and fall time of the circuit. All the results and calculations are simulated on s-edit using TANNER v.7 technology.

Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique

Background/Objectives: As technology scaling down, subthreshold operation is playing a vital role in the design of digital circuits to achieve ultra low power consumption with considerable performance. Methods/Statistical Analysis: This paper presents a novel body bias technique, where the body terminal of NMOS is reverse biased to VDD which reduces the subthreshold leakage. The basic logic gates are designed using proposed body bias scheme. To analyze the performance, standard 28 transistor full adder cell is implemented using the proposed technique and the performance parameters - power, delay, PDP are calculated and compared with the conventional CMOS Full adder. The simulations are done in cadence 90 nm technology for VDD = 0.2v. Findings: The simulation results show that the circuits designed using the proposed technique achieves more than 31% savings in power and more than 15% savings in PDP than traditional body bias technique used in static CMOS configuration. Applications/Improvements: These circuits are widely applicable in portable battery operated devices such as cellular phones, wearable electronics and remote sensors where ultra low power consumption is required with low to medium performance.

Design, implementation and performance comparison of multiplier topologies in power-delay space

With the advancements in the semiconductor industry, designing a high performance processor is a prime concern. Multiplier is one of the most crucial parts in almost every digital signal processing applications. This paper addresses the implementation of an 8-bit multiplier design employing CMOS full adder, full adder using Double Pass Transistor (DPL) and multioutput carry Lookahead logic (CLA). DPL adder avoids the noise margin problem and speed degradation at low value of supply voltages associated with complementary pass transistor (CPL) logic circuits. Multioutput carry lookahead adder leads to significant improvement in the speed of the overall circuitry. The investigation is carried out with simulation runs on HSPICE environment using 90 nm process technology at 25 °C. Finally, the design guidelines are derived to select the most suitable topology for the desired applications. Investigation reveals that multiplier design using multioutput carry lookahead adder proves to be more speed efficient in comparison with the other two considered design strategies.

Low Power CMOS Look-Up Tables using PROM

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm 2 layout area, which is less compared with 765.5 μm 2 produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

Implementation of CMOS Full Adder with Less Number of Transistors for Full Swing Output

Implementation of CMOS Full Adder with Less Number of Transistors for Full Swing Output

Comparative Analysis of Low Power 1-Bit CMOS Full Adder at 45 nm Technology

Design and simulation of conventional CMOS full adder using 45nm technology at specified node has been presented here. This research work shows comparison about post layout simulations of designed low power CMOS full adder. It also explains about performance analysis of optimized low power CMOS full adder at different loads. This design has achieved 63.11nW active power consumption with propagation delay of 0.254ns and having leakage current of 0.798nA at the supply voltage of 0.7V. Cadence’s virtuoso tool has been used for circuit design.

Low power 18T pass transistor logic ripple carry adder

In this paper, a high-speed low-power 18T CMOS full adder design featuring full-swing output is proposed. The adder is designed and simulated using pass transistor logic of the 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 22 × 10−18 J, which is a marked improvement of 61% to 98% compared against those of the 28T conventional CMOS, 20T transmission gate (TGA), 16T transmission function (TFA), 14T hybrid, 24T hybrid pass logic with static CMOS, and 28T differential pass logic (DPL) full adders simulated with the same process technology. Its power consumption is lower by 32% to 85%, with speed performance comparable to those of other high-speed adders reported in the literature. Occupying an aerial footprint of only 107 µm2 (8.00 µm × 13.41 µm), the proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation.

Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology

This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.

A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology

This paper presents two asymmetric and symmetric multi-threshold, high-speed, and energy-efficient Full Adder cells using Carbon Nanotube Field Effect Transistors (CNFETs). The utilization of unique properties to CNFETs to build structures inaccessible to MOSFETs technology is also evoked, particularly due to geometry-dependent threshold voltages ($$V_\mathrm{{th}} )$$Vth) in multiple-$$V_\mathrm{{th}} $$Vth designs to achieve high-performance circuits. In order to evaluate the proposed designs, computer simulations are carried out using 32 nm-CMOS and 32 nm-CNFET technologies. Comprehensive experiments are performed to evaluate the performance of the proposed designs using different low voltage power supplies, load capacitors, frequencies, and temperatures. Simulation results demonstrate the superiority of the proposed designs in terms of delay and power-delay product compared to the other classical and state-of-the-art CMOS and CNFET-based Full Adder cells. Moreover, in order to evaluate the robustness of the proposed symmetric cell against the variations and mismatches of both diameter of the CNTs and capacitance of input capacitors, Monte Carlo transient analysis has been carried out. Simulation results confirm that the proposed cell is robust against the mentioned fluctuations.

PERFORMANCE EVALUATION OF FULL ADDER AND ITS IMPACT ON RIPPLE CARRY ADDER DESIGN

Full adder is an essential module in the design and development of all types of processors such as digital signal processors (DSP), microprocessors etc. Adders are the nucleus element of composite arithmetic operations like addition, multiplication, division, exponentiation etc. The various full adders available are conventional CMOS full adder, parallel prefix adders, hybrid full adders, and mirror full adders, adders using transmission gates and multiplexer logic. The main goal is to compare the existing full adder circuit’s performance and to identify a Low Power Full Adder and to analyze its impact on 8-bit, 16-bit, 32-bit ripple carry adder design. Mentor Graphics IC studio tool in 180 nm technology is used to design and implement the proposed full adders and ripple carry adders.

A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

CNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder Circuits

This paper presents a novel CNFET-based design for three-input Exclusive-OR circuits as well as Full Adder cells for low-voltage and high frequency applications. These designs take advantage of high performance and low power consumption and have simple and symmetric structures. Comprehensive experiments are carried out to evaluate the performance of the proposed designs in various conditions. Simulations are performed using Synopsys HSPICE with 32 nm CMOS and 32 nm CNFET technologies. The simulation results demonstrate the superiority of the proposed structures in terms of speed, power consumption, and power-delay-product compared to other modern CMOS and CNFET-based Full Adder cells.