CMOS-compatible Techniques Research Articles

A fast-response/recovery ZnO hierarchical nanostructure based gas sensor with ultra-high room-temperature output response

In this paper, a ZnO hierarchical nanostructure based gas sensor is presented. The proposed implementation features short response/recovery time and ultra-high output response at room temperature (RT). In order to take the advantages of complementary-metal-oxide-semiconductor (CMOS) process in terms of miniaturization and cost-effectiveness, a novel fabrication recipe, consisting of CMOS-compatible techniques, is proposed to form a patterned triple-layer metal, which functions as both interconnection electrodes and catalyst for our reported ZnO hierarchical nanostructure. This enables rapid and local growth of ZnO hierarchical nanostructure directly on a single silicon chip. Reported peak RT output response of 32 (20ppm NO2) provides a significant 28-fold improvement over the traditional widely adopted nanowire-based gas sensor. Meanwhile, a time efficient gas sensor is also validated by the presented temporal performance with a response and recovery time of 72s and 69s, respectively. In addition, compared with the previously demonstrated gas sensors operating at 200–300°C, the proposed RT sensing completely removes the power-hungry heater and eliminates the related thermal reliability issues. Moreover, the demonstrated process flow well addresses the challenging issues of the traditional mainstream “drop-cast” method, including poor yield, non-uniformity of device performance and low efficiency caused by inevitable manual microscope inspection.

(Invited) UV Excimer Laser Assisted Heteroepitaxy of (Si)GeSn on Si(100)

Fabrication of Photonic Integrated Circuits (PICs) using CMOS compatible direct bandgap Group-IV heterostructures is of increasing concern from scientific, technological, and economic point of view. Growth of group IV alloys, such as the Silicon-Germanium-Tin (Si-Ge-Sn) binaries and ternaries through CMOS compatible techniques is therefore of particular interest. This contribution presents UV-Laser based processes, such as Laser induced Chemical Vapor Deposition (LCVD) and Pulsed Laser Induced Epitaxy (PLIE) combined with conventional processing techniques, for material synthesis as well as results obtained growing different (Si)GeSn binary and ternary systems for material and lattice engineering. Synthesis of epitaxial (Si)GeSn alloys with above 10% Sn in large areas and of SiGeSn/GeSn micropatterns, through scanning and mask projection assisted PLIE, respectively, will be discussed. Emphasis will be placed on the influence of processing parameters on compositional and structural properties of the epitaxial alloys.

33.3L: Late‐News Paper: Optimizing Nanostructures to Enhance Optical Outcoupling of OLED Microdisplays

AbstractWe present optical simulations of a nanostructured OLED‐anode design to enhance the optical outcoupling efficiency. The design allows for the integration of a grating structure with high refractive index contrast into top‐emitting OLED microdisplays using CMOS‐compatible techniques.

Detecting Interleukin-1β Genes Using a N2O Plasma Modified Silicon Nanowire Biosensor

Background Developing ultrasensitive and selective biological sensors has increased in interest for applications in disease detection, drug discovery, and biomedical diagnostics. This paper reports a CMOS-compatible technique for fabricating a silicon nanowire field-effect transistor. The nanowire sensor was applied to detect a fragment of the cancer-related interleukin-1β (IL-1β) gene, which is characterized as an indicator of breast, colon, lung, oral, head, and neck cancers. Methods We used the advanced integrated circuit (IC) technique to fabricate a back-gated nanowire field-effect transistor sensor. The dimensions of the nanowire were 60 nm in width and 20 μm in length. To enhance the sensitivity of the nanowire sensor, a plasma modification treatment with various parameters was employed on the surface of the device. Results The sensitivity of the silicon nanowire field-effect transistor could be improved after a 1-minute N2O plasma treatment, because the morphology of the detection region is rougher after the N2O plasma treatment. Hence, a more functional linker could be bound to the surface, thereby increasing the probability of DNA immobilization and hybridization. We used a specific sequence of the IL-1β gene to verify the sensitivity enhancement of the nanowire sensor by using plasma treatment. Conclusion The sensitivity and detection limit of the plasma-treated sensor can be extrapolated to 0.12/decade and 2.5fM, respectively. The detection results demonstrate that real-time monitoring of the expression of IL-1β using nanowire sensors could be useful for evaluating cancer treatment.

Localized growth and in situ integration of nanowires for device applications

Simultaneous localized growth and device integration of inorganic nanostructures on heated micromembranes is demonstrated for single crystalline germanium and tin oxide nanowires. Fully operating CO gas sensors prove the potential of the presented approach. With this simple CMOS compatible technique, issues of assembly, transfer and contact formation are addressed.

Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

This letter, for the first time, reports a high-density silicon-nanowire (SiNW)-based thermoelectric generator (TEG) prepared by a top-down CMOS-compatible technique. The 5 mm × 5 mm TEG comprises of densely packed alternating n- and p-type SiNW bundles with each wire having a diameter of 80 nm and a height of 1 μm. Each bundle serving as an individual thermoelectric element, having 540 × 540 wires, was connected electrically in series and thermally in parallel. The fabricated TEG demonstrates thermoelectric power generation with an open circuit voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oc</sub> ) of 1.5 mV and a short circuit current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> ) of 3.79 μA with an estimated temperature gradient across the device of 0.12 K.

Ultrasensitive nanowire pressure sensor makes its debut

A membrane pressure sensor with embedded piezoresistive silicon nanowires (NW) has been demonstrated to have an ultrasensitive piezoresistive response of (ΔR/R)/ΔP of 13 Pa−1. This was achieved through the effective tuning of the transverse electric field across the NW. The fabrication of the sensor is fully based on CMOS compatible technique. P-type 〈110〉 oriented NWs with a square cross-section of 100 nm were fabricated on silicon-on-insulator (SOI) wafers, acting as the sensing elements. The NWs’ exceptional properties and minute size will enable further shrinking of footprint of pressure sensors and other NEMS sensors with increased sensitivity, opening a way to new applications like implantable medical devices.

Ultra-sensitive detection of adipocytokines with CMOS-compatible silicon nanowire arrays

Perfectly aligned arrays of single-crystalline silicon nanowires were fabricated using top-down CMOS-compatible techniques. We demonstrate that these nanowire devices are able to detect adipocytokines secreted by adipose cells with femtomolar sensitivity, high specificity, wide detection range, and ability for parallel monitoring. The nanowire sensors also provide a novel tool to reveal the poorly understood signaling mechanisms of these newly recognized signaling molecules, as well as their relevance in common diseases such as obesity and diabetes.

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

850 nm wavelength range nanoscale resonant optical filter fabrication using standard microelectronics techniques

The fabrication and characterization of a nanoscale resonant optical filter at wavelength around 850 nm is reported using standard C-MOS compatible microelectronics techniques. We discuss the different steps of the process and their impact on the final structure. We show that the use of these techniques gives an efficient filter on glass substrate with high transmission and a narrow bandwidth of 0.4 nm. We also demonstrate the same process on a silicon substrate for a potential integration with electronic functions.

Blazed GxL™ device for laser dream theatre at the Aichi expo 2005

A blazed GxL™ device is described as having high optical efficiency (> 70% for RGB lasers), and high contrast ratio (> 10,000:1), and that is highly reliable when used in a large‐area laser projection system. It has a robust design and precise stress control technology to maintain a uniform shape (bow and tilt) of more than 6,000 ribbons, a 0.25‐μm CMOS compatible fabrication processing and planarization techniques to reduce fluctuation of the ribbons, and a reliable Al‐Cu reflective film that provided protection against a high‐power laser. No degradation in characteristics of the GxL device is observed after operating a 5,000‐ lumen projector for 2,000 hours and conducting 2,000 temperature cycling tests at ‐20°C and +80°C. At the 2005 World Exposition in Aichi, Japan the world's largest laser projection screen with a size of 2005 inches (10 m × 50 m) and 6 million pixels (1,080 × 5,760) was demonstrated.

Carbon Nanotube Micro-Opto-Mechanical Grippers

ABSTRACTWe report the integration of single wall carbon nanotube ensembles into micro-mechanical systems to realize a new carbon nanotube micro-optomechanical system (CNT-MOMS). CNT-MOM grippers were fabricated with CMOS compatible techniques involving nanotube film formation, wafer bonding, photo-lithography, plasma etching and dry release. MOM-grippers displacement of ∼24μm was obtained from a gripper of 430μm in length under infra-red laser stimulus and continuous operation of more than 100,000 cycles was acquired. The optical power consumption of the gripper operation was estimated to be as small as ∼240μW. This study is a good example of how nano-materials could be integrated into CMOS compatible techniques for applications in high performance MEMS and nanoscale actuation technologies.

SOI-CMOS compatible low-power gas sensor using sputtered and drop-coated metal-oxide active layers

In this paper, a Silicon-On-Insulator (SOI) solid-state gas-sensor with an original design of a polysilicon loop-shaped microheater fabricated on a thin-stacked dielectric membrane is presented. The microheater ensures high thermal uniformity and very low power consumption (25 mW for heating at 400°C). Sensitive films are based on tin and tungsten oxides deposited either by RF sputtering or drop coating methods. The fabricated sensors are tested to a wide variety of contaminant species and promising results are obtained. The use of completely CMOS compatible TMAH-based bulk micro-machining techniques during the fabrication process, allows easy smart gas sensor integration in SOI-CMOS technology. This makes SOI-based gas-sensing devices particularly attractive for use in handheld battery-operated gas monitors.

SOI CMOS Compatible Low-Power Microheater Optimization for the Fabrication of Smart Gas Sensors

In this paper, an original design of a polysilicon loop-shaped microheater on a 1-/spl mu/m thin-stacked dielectric membrane is presented. This design ensures high thermal uniformity and insulation and very low power consumption (20 mW for heating at 400/spl deg/C). Moreover, the use of completely CMOS compatible tetramethyl ammonium hydroxide-based bulk-micromachining techniques allows an easy, smart gas sensor integration in SOI-CMOS technology.

CMOS-Compatible Micromachined Edge-Suspended Spiral Inductors With High Q-Factors and Self-Resonance Frequencies

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.

Flexible polyimide-based intracortical electrode arrays with bioactive capability.

The promise of advanced neuroprosthetic systems to significantly improve the quality of life for a segment of the deaf, blind, or paralyzed population hinges on the development of an efficacious, and safe, multichannel neural interface for the central nervous system. The candidate implantable device that is to provide such an interface must exceed a host of exacting design parameters. We present a thin-film, polyimide-based, multichannel intracortical Bio-MEMS interface manufactured with standard planar photo-lithographic CMOS-compatible techniques on 4-in silicon wafers. The use of polyimide provides a mechanically flexible substrate which can be manipulated into unique three-dimensional designs. Polyimide also provides an ideal surface for the selective attachment of various important bioactive species onto the device in order to encourage favorable long-term reactions at the tissue-electrode interface. Structures have an integrated polyimide cable providing efficient contact points for a high-density connector. This report details in vivo and in vitro device characterization of the biological, electrical and mechanical properties of these arrays. Results suggest that these arrays could be a candidate device for long-term neural implants.

A novel insulation technique for smart power switching devices and very high voltage ICs above 10 kV

In this paper we will present a new CMOS compatible integration technique which will allow an integration of smart power switching devices and HV ICs with operating voltages above 10 kV. With an improved etching technique on standard silicon wafers all devices (low voltage and high voltage) can be integrated in the same silicon substrate at the same time. Since yet other researchers have integrated HV ICs in SOI films or in high resistive material with maximum blocking voltages of 1400 V so far [1]. High voltage switching devices are only available with switching currents above several amperes on a large device area. Measurements of our monolithicaly integrated low current HV devices with blocking voltages of more than 10 kV on a small chip area of about 45 mm 2 will be presented.

Semiconducting YBaCuO pyroelectric infrared detectorson suspended Si 3 N 4 films

Uncooled, micromachined pyroelectric infrared detectors based on semiconducting YBaCuO were fabricated and characterised at room temperature. The detectors were fabricated with CMOS compatible techniques that demonstrate a future ability to fabricate low-cost focal plane arrays. Pyroelectric coefficients were measured to be as high as 4.1 µC/cm2 K and detectivities over 108 cm·Hz1/2/W were measured.