CMOS Bandgap Voltage Reference Research Articles

A sub-1V high PSRR OpAmp based β-multiplier CMOS bandgap voltage reference with resistive division

<span lang="EN-US">A sub-1V opamp based β-multiplier CMOS bandgap voltage reference (BGVR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed in this paper. A current mode regulator scheme is inserted to isolate the supply voltage of the operational amplifier (opamp) and the supply voltage of the BGVR core from the supply voltage source in order to reduce ripple sensitivity and to achieve a high PSRR. The proposed circuit is designed and simulated in 0.18-μm standard CMOS technology. The proposed voltage reference delivers an output voltage of 634.6mV at 27°C. Tthe measurement temperature coefficient is 22,3ppm/°C over temperature range -40°C to 140°C, power supply rejection ratio is -93dB at 10kHz and -71dB at 1MHz and a line regulation of 104μV/V is achieved over supply voltage range 1.2V to 1.8V. The layout area of the proposed circuit is 0.0337mm<sup>2</sup>. The proposed sub-1V bandgap voltage reference can be used as an internal voltage reference in low power LDO regulators and switching regulators.</span>

A 1.8 V 0.918 ppm/°C CMOS bandgap voltage reference with curvature-compensated

A 1.8 V 0.918 ppm/°C CMOS bandgap voltage reference with curvature-compensated

A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

A resistorless high-precision compensated CMOS bandgap voltage reference (BGR), which is compatible with a standard CMOS process, is presented in this paper. A higher-order curvature correction method called base-emitter voltage linearization is adapted to directly compensate the thermal nonlinearity of base–emitter voltage. With proper mathematical operations of high-order temperature currents, most of the nonlinear temperature terms in $V_{\mathrm {BE}}$ can be greatly eliminated. The proposed BGR, which is implemented in 0.35- $\mu \text{m}$ CMOS technology, is capable of working down to 2 V supply voltages with 1.14055 V mean output voltage. A minimum temperature coefficient of 1.01 ppm/°C with a temperature range from −40 °C to 125 °C is realized, and a power-supply noise attenuation of 61 dB is achieved without any filter capacitors. The line regulation is better than 2 mV/V from 2 V to 5 V supply voltage while dissipating a maximum supply current of $33~\mu \text{A}$ . The active area of the presented BGR is 180 $\mu \text {m}\times 220\,\,\mu \text{m}$ .

A 3.3 V, 8.89 μA and 5.5 ppm/°C CMOS bandgap voltage reference for power telemetry in retinal prosthesis systems.

A 3.3 V CMOS bandgap reference (BGR) was presented in this study that utilizes MOS transistors operating in the sub-threshold region. The complexity of the circuit and the dependency of the voltage reference on power supply variations are simultaneously decreased through the use of a new compensation circuit technique. The proposed BGR is simulated using a 0.35 $\mu \mathrm{m}$ CMOS standard process. Consequently, a 5.53 ppm/°C temperature coefficient is obtained in the -40~+125 °C temperature range, the maximum power supply rejection ratio is - 62 dB, and a 2.033 mV/V voltage line regulation is achieved for the $2.3\sim 4.3$ V supply voltage. The proposed circuit dissipates a supply current of 8.89 IJA at a 3.3 V supply voltage, and the active area is 112 $\mu \mathrm{m}\times 60 \mu \mathrm{m}$.

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- $\mu \text{m}$ CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V reg for the BG core and Op-Amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.

CMOS 소자로만 구성된 1V 이하 저전압 저전력 기준전압 발생기

본 논문에서는 저항과 BJT를 사용하지 않고 sub-threshold 영역에서 동작하는 저전압, 저전력 기준전압 발생기를 설계하였다. CTAT 전압 발생기는 두 개의 NMOS 트랜지스터를 이용하여 구성하였고, 충분한 영역의 CTAT 전압을 발생시키기 위해 바디 바이어스 회로를 이용하였다. PTAT 전압 발생기는 PTAT 전압을 생성하기 위해 MOS 트랜지스터 입력 쌍의 서로 다른 사이즈 비를 이용하는 차동증폭기 형태로 구성하였다. 제안한 회로는 <TEX>$0.18-{\mu}m$</TEX> 표준 CMOS 공정으로 설계되었다. 시뮬레이션 결과로 290mV의 출력 기준 전압을 가지며, -<TEX>$20^{\circ}C$</TEX> 에서 <TEX>$120^{\circ}C$</TEX>의 온도 변화에서 92 ppm/<TEX>$^{\circ}C$</TEX>의 전압 변화 지수와 전원전압 0.63V에서 15.7nW의 소모 전력을 갖는 것을 확인하였다. In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/<TEX>$^{\circ}C$</TEX> in -20 to <TEX>$120^{\circ}C$</TEX> temperature range. The circuits consume 15.7nW at 0.63V supply.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio (high-PSRR) high-order curvature-compensated CMOS bandgap voltage reference (BGR) in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvature- corrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T1.5 current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42×10−6/°C from −55 °C to 125 °C with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of −123.51 dB, −123.52 dB, −88.5 dB and −50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.

A sub 1V CMOS bandgap reference with two diodes

A small size, sub 1V CMOS bandgap voltage reference with the temperature coefficient (TC) of 12ppm/°C from 0°C to 100°C is presented in this paper. The proposed circuit offers several performance advantages over previous bandgap voltage reference circuits. Compared to a conventional structure, it achieves a smaller area by using only two diodes. Also, it can fulfil sub 1V reference voltage by using temperature coefficient of threshold voltage to generate a current proportional to absolute temperature. This is because TC of this current on proposed circuit is bigger than that of conventional structure. Detailed analysis of the proposed bandgap reference is provided, which is simulated using 0.35μm CMOS process. The proposed bandgap reference occupies an active area of 0.0067mm2. The simulation results are the voltage reference output voltage of 0.843V and an accuracy of ±0.08%.

Analysis and Experimental Study of the Package Stresses in a QFN Plastic-Encapsulated Package

Plastic-encapsulated packages are known to suffer package stress issues which often cause undesired shifts in the IC electrical parameters. Two types of package stress are analyzed and their contributions to the overall package stress in a Quad-Flat No-leads (QFN) Package are experimentally studied in this paper. The volumetric package stress generated by the mold compound is analyzed using the material properties of the bulk modulus and the volumetric coefficient of thermal expansion (vCTE). The in-plane package stress generated by the die and the die-attach material is analyzed using the structural analysis method with the introduction of an improved Suhir solution to evaluate the in-plane normal stress at the active area of the IC die. These theoretical analysis results are further experimentally studied with the functional measurements on a precision CMOS bandgap voltage reference in a QFN package. Using the combination of two different die-attach methods and two different die-coating conditions, the parametric variations in the bandgap voltage can be correlated with the different types of package stress. The actual test data presented in this paper are in good agreement with the theoretical analysis results.

Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references

A novel resistorless bipolar junction transistor (BJT) bias and curvature compensation circuit for ultra-low-power CMOS bandgap voltage references (BGRs) is introduced. It works in the nanoampere current consumption range and under 1 V of power supply. The analytical behaviour of the circuit is described and simulation results for a 0.18 μm CMOS standard process are analysed. A junction voltage of 550 mV at room temperature is obtained (at an emitter current of 3.5 nA), presenting an almost linear temperature dependence, whereas the power consumption of the whole circuit is 3.4 nW under a 0.8 V power supply at 27°C. The estimated silicon area is 0.00135 mm 2 .

A 1.6 ppm/°C bandgap voltage reference for an extended operating temperature range

A new CMOS bandgap voltage reference (BGR) is proposed and simulated using Silterra 0.13 μm CMOS technology. The proposed BGR utilizes 3 curvature-corrected current generators that compensate for the output voltage variation in an extended temperature range. The proposed circuit generates an output voltage of 1.181 V with a variation of 380 μV from !50 °C to 150 °C.

Design and Implementation of Op-Amp Based Low-Power CMOS Bandgap Voltage Reference with Minimum Supply oF 0.8-V

A low power voltage source is generated by altering the device size in existing topology has been presented. Bandgap voltage reference is generated by combination of start-up, supply independent, operational amplifier (Op-amp) and bandgap core circuits which has been designed such that low sensitivity of temperature and supply variation. It has been designed with minimum supply of 0.8 V without use of low threshold device, and the maximum supply current is 35 µA. It has been implemented in 180 nm standard digital CMOS Process. The circuit generates a reference voltage of 540 mV and has a temperature coefficient of 14 ppm /°C from −40 °C to 120 °C. The generated reference voltage is independent of temperature and supply variations have been mathematically proved by analyzing the circuit design. Also, proper selection of on-chip passive components and its values has been chosen which is based on low noise. Comparing the pre and post layout simulation results has been presented.

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

ABSTRACTThis paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (tox &lt; 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, TC_AVG, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (TC_AVG = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley &amp; Sons, Ltd.

개선된 CTAT 보상을 가지는 저전압 CMOS Bandgap Voltage Reference

In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn"t use PTAT current. The proposed structure is more simple than the existing structure and doesn"t use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12ppm/°C from 0°C to 100°C.

A simple curvature-compensated technique for CMOS bandgap voltage reference

A simple high-order curvature-compensated technique for CMOS bandgap voltage reference (BVR) is presented and its advantage over the conventional ones is that this technique needs no extra circuitry for curvature compensation. The experimental prototype circuit is fabricated in CSMC 0.18µm CMOS process and occupies an area of 0.053mm2. A temperature coefficient (TC) of 10.1ppm/°C is achieved with temperature ranging from -40°C to 120°C under 3V power supply. The line regulation of the output reference is only 0.85mV/V.

Sub 1 V CMOS bandgap reference design techniques: a survey

This paper presents a review of constraints, limitation factors and challenges to implement sub 1 V CMOS bandgap voltage reference (BVR) circuits in today’s and future submicron technology. Moreover, we provide insight analysis of BVR circuit architectures a designer can relay upon when building CMOS voltage reference.

An area and power optimization technique for CMOS bandgap voltage references

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in the technology and also the area of bipolar transistors. The proposed technique does not depend on a special process and can be applied for designing bandgap reference circuits with different topologies.

A [formula omitted] CMOS bandgap reference featuring a 1.5–6 mA output driving current and a Miller-effect startup circuit

We present a pure CMOS bandgap voltage reference with a low quiescent current and high output current driving capability. The circuit sources a driving current of up to 1.5mA with the reference voltage kept above 98.5% of its designated 1.2V, and up to 6mA before the voltage drops to 90%. The circuit achieves a very low supply current of 13μA, a low power of 30μW, a line regulation of ±2.5mV/V and a load regulation of ±7mV/mA. The reference is implemented in a 1μm pure CMOS process with Vtn≈|Vtp|≈0.7V at 25∘C using substrate pnp. A startup circuit, which shuts down itself after a controlled delay using Miller effect, is also introduced. By utilizing the body effect of the input transistors, the turn-on threshold of the startup circuit is raised to about 1V, making it a perfect match for the reference architecture. Silicon measurements are in good agreement with simulations.

A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm x 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from-10°C to 120°C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10kHz.