Analog CMOS Circuits Research Articles

A Novel Dung Beetle Optimization Approach for Automatic CMOS Analog Circuit Design

The main objective of the automated circuit sizing technique is to deal with the challenges of design tradeoffs in analog circuit design with improved accuracy and efficacy. Analog circuit design represents a multi-objective optimization challenge, where designers must properly balance various performance factors such as input and output impedance, power dissipation, area, unity-gain bandwidth, slew rate, and open-loop DC gain. Traditional design equations provide a sizing of differential amplifier MOS transistors, further optimization can be achieved through the application of meta-heuristic search techniques. Meta-heuristic search techniques can be used as local optimizers in a smaller search area to improve the optimization of design parameters. The differential amplifier circuit with current mirror load is optimized through the application of the Dung Beetle Optimization (DBO) algorithm. By using an evolutionary algorithm called DBO, all the required parameters were achieved with the least amount of transistor area and power dissipation when compared to the results of the Seeker Optimization Algorithm (SOA), Opposition based Harmony Search Algorithm (OHS), craziness-based particle swarm optimization (CRPSO), and Cuckoo Search (CS) algorithms.

A Memristor Crossbar-Based Lyapunov Equation Solver

An analog memristor crossbar based Lyapunov equation solver is proposed in this paper. It is an extension of memristor crossbar linear equation solver, but taking into account of the regularity with Lyapunov equation in the organization of crossbar. Nonideal effects due to co-design with CMOS analog circuits are studied in detail. Verification using a Verilog-AMS tool is performed to justify that with proper scaling on the memristor conductance values and other circuit signals, the solution quality of Lyapunov matrix equation can be improved.

Aging Compensation in a Class-A High-Frequency Amplifier with DC Temperature Measurements.

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration.

Fault Coverage Improvement of CMOS Analog Circuits Using Supply Current Testing Method

In this paper, a testing technique based on supply current verifying is presented, for fault detection of analog circuits containing CMOS operational amplifiers. This testing technique is employed and developed to maximize the fault coverage of the circuit under test (CUT) using transient and frequency responses of the supply current. This testing method is based on the over-sighting of the quiescent supply current (Iddq) of the CMOS operational amplifier operating in its quiescent mode and the supply current of the CMOS operational amplifier used as a Sallen-Key band pass filter in the AC and transient operating domains. The faults investigated in our study are of bridging and open circuit types that occur at the CMOS transistor level. The Pspice software was used for the CUT simulation by applying Monte-Carlo analysis in faulty and fault free conditions. Test parameters are extracted and selected to be used as input features of our classifier.

New CMOS Linear Transconductors and their Applications

The object of this paper is to introduce a new CMOS differential input single output (DISO) transconductor (realizable from eight MOSFETs operating in saturation) and a dual input dual output (DIDO) transconductor (realizable with 16 MOSFETs operating in saturation) and their applications in realizing grounded/ floating, positive/ negative, electronically controllable resistors and inductors. The workability of all the prepositions has been demostrated by SPICE simulations using TSMC 0.18[Formula: see text] m CMOS technology parameters. The paper, thus, adds a number of useful electronically-controllable circuits to the existing repertoire of CMOS analog circuits for signal processing.

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction.

Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

Machine learning‐based design automation of CMOS analog circuits using SCA‐mGWO algorithm

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

A NOVEL APPROACH FOR THE DESIGN AUTOMATION OF CMOS ANALOG CIRCUITS USING HYBRID SCAmGWO ALGORITHM

The widespread use of consumer electronics has made the automation of analog design process inevitable for integrated circuits (ICs) for reduction in the overall time-to-market. In this paper, a novel tool for automated component sizing of CMOS analog circuits is presented using a novel hybrid of sine-cosine algorithm and modified grey wolf optimization algorithm (SCAmGWO) in the optimization section of the automation process. The proposed tool uses the interface of two tools, i.e., CADENCE for accurate model simulation and MATLAB for optimization of parameters using the results from CADENCE, in a loop. The performance of the proposed algorithm is evaluated using a set of different benchmark functions along with comparison. Further, a rigorous performance evaluation is also done with over 20 independent runs and a Wilcoxon rank-sum test. The performance of the proposed algorithm is evaluated with a conventional two-stage operational amplifier as benchmark. The operational amplifier implemented in CADENCE design environment, with 180 nm as standard CMOS technology, uses the aspect ratios calculated by simulating program in MATLAB using 180 nm CMOS standard process. The exploration and exploitation ability of the hybrid algorithm is improved by tailoring the advantages of two algorithms, i.e., sine-cosine algorithm and modified grey wolf optimization algorithm. To prove its acute existence, a statistical study over 20 independent runs is also performed. An overall comparison of the solution with other competing sizing tools proves its efficiency. The immutability of the design obtained using SCAmGWO algorithm is also validated using Monte Carlo simulation and corner analysis.

Application of improved ACM model to the design by hand of CMOS analog circuits

This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware.

Any large-scale spiking neuromorphic system striving for complexity at the level of the human brain and beyond will need to be co-optimized for communication and computation. Such reasoning leads to the proposal for optoelectronic neuromorphic platforms that leverage the complementary properties of optics and electronics. Starting from the conjecture that future large-scale neuromorphic systems will utilize integrated photonics and fiber optics for communication in conjunction with analog electronics for computation, we consider two possible paths toward achieving this vision. The first is a semiconductor platform based on analog CMOS circuits and waveguide-integrated photodiodes. The second is a superconducting approach that utilizes Josephson junctions and waveguide-integrated superconducting single-photon detectors. We discuss available devices, assess scaling potential, and provide a list of key metrics and demonstrations for each platform. Both platforms hold potential, but their development will diverge in important respects. Semiconductor systems benefit from a robust fabrication ecosystem and can build on extensive progress made in purely electronic neuromorphic computing but will require III-V light source integration with electronics at an unprecedented scale, further advances in ultra-low capacitance photodiodes, and success from emerging memory technologies. Superconducting systems place near theoretically minimum burdens on light sources (a tremendous boon to one of the most speculative aspects of either platform) and provide new opportunities for integrated, high-endurance synaptic memory. However, superconducting optoelectronic systems will also contend with interfacing low-voltage electronic circuits to semiconductor light sources, the serial biasing of superconducting devices on an unprecedented scale, a less mature fabrication ecosystem, and cryogenic infrastructure.

A Compact Low-Power CMOS Analog FSR Model-Based CNN

A compact low-power CMOS analog circuit implementation of a Cellular Neural Network based on Full Signal Range Model (FSR-CNN) is presented. The required operations in cell definition are synapses (multiplication and summation) and saturated integration. In each synapse, a new multiplier architecture is employed with voltage and current inputs and a current output, which allows sharing building blocks and using continuously programmable weight values. Feasibility and usefulness of the proposed FSR cell architecture is verified through the simulation of two applications: the connected component detector and the border extractor.

Gate Electrode Material Effect on Characteristics of Zirconium-Doped Hafnium Oxide High-k MOS Capacitors

The hafnium oxide based high-k dielectric material has been used to replace SiO2 in advanced MOSFETs to lower down the leakage current based on the same equivalent oxide thickness (EOT) of SiO2 [1,2]. The Zr-doped HfO2 (ZrHfO) thin film has many advantages over the undoped HfO2 thin film with respect to the higher permittivity, higher crystallization temperature, lower interface thickness, and lower interface density of states [3-6]. MOS capacitors with EOT less than 1 nm has been successfully prepared using the sputter deposited ZrHfO [5]. The metal electrode material is crucial to the device performance because it could diffuse into the structure to introduce dipoles or new charge trapping sites [7,8]. In this paper, electrical properties of MOS capacitors made of two different gate electrode materials, i.e., copper (Cu) and molybdenum (Mo), were investigated.MOS capacitors were fabricated on p-type Si (100) 1015 cm-3 wafers. The ZrHfO film was sputtered deposited from a Zr/Hf (12/88 wt. %) target under Ar/O2 (1:1 sccm) at 10 mTorr and 80 W for 12 min. The sample was subsequently annealed at 800°C in N2 for 5 min. Then, a 200 nm thick Cu or Mo electrode film was sputter deposited at 10 mTorr and 80 W, i.e., 20 min for the former and 120 min for the latter. They were etched into round gate electrodes of 200 µm, 300 µm and 400 µm diameters. The Mo electrode was wet etched with a H3PO4/HNO3/CH3COOH/H2O (80:5:5:10) solution. The Cu electrode was etched with a plasma-based etch process of which the detailed process condition can be found in refs [9]. Then, the sample was treated with a post metal annealing (PMA) step at 250°C in N2 for 10 min. Samples without the PMA treatment, i.e., controlled samples, were also prepared and measured for comparison. Electrical properties, e.g., EOT, VFB , Dit , and Qot , of the sample were extracted from the C-V curve using the method described in ref 10.Figure 1 shows the C-V hysteresis curves of Mo gated capacitors (a) before and (b) after PMA. The samples were measured with the gate voltage (Vg ) swept from -3 V to 3 V (forward) and then back to -3 V (backward). The control sample shows a large flat-band voltage shift ( ) of 1.4881 V while the annealed sample shows a much smaller ’s of 0.083 V. Also, the Qot is decreased from 9.611011 to 1.091011 cm-2 for the control and annealed samples [10]. The long Mo sputtering time may induce hole-trapping defects in the high-k film or at the high-k/Si interface. In addition, it was reported that the Mo gate could react with high-k film to form new bonds that reduced the work function [11]. The 250˚C annealing step can effectively reduce defects in various parts of the capacitor.Figure 2 shows the C-V hysteresis curves of Cu gated capacitors (a) before and (b) after PMA. Before PMA, the C-V curve is similar to that of a good capacitor with a low of 0.012 V, which corresponds to a low charge trapping density [10]. However, after PMA, the C-V curve distorted. It shows the strong inversion phenomenon, which indicates the possible high electron concentration at the interface exceeding the dopant concentration near the wafer interface [12]. Since Cu can easily diffuse through a dielectric film [13], it is possible that Cu diffuses through the high-k gate dielectric during the PMA step. Cu in the high-k film may exist in the CuOx form, which changed the charge trapping states and locations. More discussions on the above mechanism will be presented.Lingguang Liu acknowledges the financial support of National Natural Science Foundation of China (Grant Number:61771382), China Scholarship Council (No. 201806280283) and the Shaanxi International Science and Technology Cooperation and Exchange Program (2018KW-034). 1. Kang, et al., IEEE EDL, 21, 181 (2000).2. I. Hegde, et al., JAP, 101, 074113 (2007).3. Kuo, ECST, 3, 253 (2006).4. Kuo, et al., ECST, 1, 447 (2006).5. Yanet al., ECS SSL, 10, H199 (2007).6. Luo, et al., APL, 89,072901 (2006).7. Ravindran, et al., APL, 89, 263511 (2006).8. C. Vezzoli, et al., Ceram. Int., 23, 105 (1997).9. Kuo and S. Lee,APL, 78, 1002 (2001).10. H. Nicollian and J. R. Brews, MOS Physics and Technology, p424, Wiley, New York (1982).11. Ha, et al., JJAP, 42, 1979-1982 (2003).12. Ytterdal, et al., Device Modeling for Analog and RF CMOS Circuit Design, p4, Wiley (2003).13. D. McBrayer, et al.,JES, 133, 6,1242 (1986). Figure 1

Convergence rates of the efficient global optimization algorithm for improving the design of analog circuits

Optimal sizing of analog circuits is a hard and time-consuming challenge. Nowadays, analog designers are more than ever interested in developing solutions for automating such a task. In order to overcome well-known drawbacks of the conventional equation-based and simulation-based sizing techniques, analog designers are being attracted by the so-called metamodeling techniques and recently have used them for establishing accurate models of circuits’ performances. Metamodels have been associated to optimization routines to maximize circuits’ performances. In this work we deal with the newly proposed efficient global optimization (EGO) algorithm that intrinsically offers both the metamodel generation and the optimization routine. Furthermore, it performs the requested task by using a relatively very small number of performance evaluations. Firstly, we focus on the convergence rates of the EGO technique via twenty benchmark test problems. Then, we use EGO for the optimal design of a couple of analog CMOS circuits. Comparison between EGO performances and those obtained using two surrogate-assisted metaheuristics is provided to show potentialities of the proposed approach. Finally, The case of muti-objective problems is also considered. The multi-objective efficient global optimization algorithm is used for generating Pareto fronts of conflicting perormances of two analog circuits. Obtained results are compared to those of the conventional in-loop optimization technique.

1/f Noise Modelling and Characterization for CMOS Quanta Image Sensors

This work fits the measured in-pixel source-follower noise in a CMOS Quanta Image Sensor (QIS) prototype chip using physics-based 1/f noise models, rather than the widely-used fitting model for analog designers. This paper discusses the different origins of 1/f noise in QIS devices and includes correlated double sampling (CDS). The modelling results based on the Hooge mobility fluctuation, which uses one adjustable parameter, match the experimental measurements, including the variation in noise from room temperature to –70 °C. This work provides useful information for the implementation of QIS in scientific applications and suggests that even lower read noise is attainable by further cooling and may be applicable to other CMOS analog circuits and CMOS image sensors.

Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach

This article proposes an efficient approach to design two different CMOS analogue circuits, namely p-channel Metal-Oxide-Semiconductor (PMOS) driver-based two-stage comparator and n-channel Metal-Oxide-Semiconductor (NMOS) driver-based folded-cascode operational amplifier, using a modified version of particle swarm optimization (PSO) known as craziness-based PSO (CRPSO) algorithm. PSO replicates the behaviour of bird flocking, and it requires a fewer number of control parameters. The drawbacks of PSO are premature convergence and stagnation problem. Due to these drawbacks, the PSO is improved to CRPSO for the optimal design of analogue circuits. The near-global optimal solution has been achieved by using the CRPSO. The CRPSO is used to attain the optimal sizes of the MOS devices for the individual circuits, which lead to the minimization of the total MOS area occupied by the circuit. SPICE simulation has also been carried out with the optimal device dimensions achieved from the CRPSO algorithm. Statistical analysis and the process corner analysis have also been performed for the above mentioned circuits. SPICE-based results confirm that the CRPSO-based approach is a better technique compared to the other earlier reported methods for both the circuits.

Parameter Space Exploration for Analog Circuit Design Using Enhanced Bee Colony Algorithm

In this work, novel swarm optimization algorithm based on the Artificial Bee Colony (ABC) algorithm called Enhanced Artificial Bee Colony (EABC) algorithm is proposed for the design and optimization of the analog CMOS circuits. The new search strategies adopted improve overall performance of the proposed algorithm. The performance of EABC algorithm is compared with other competitive algorithms such as ABC, GABC (G-best Artificial Bee Colony Algorithm) and MABC (Modified Artificial Bee Colony Algorithm) by designing three CMOS circuits; Two-stage operational amplifier, low-voltage bulk driven OTA and second generation low-voltage current conveyor in 0.13 [Formula: see text]m and 0.09[Formula: see text][Formula: see text]m CMOS technologies. The obtained results clearly indicate that the performance of EABC algorithm is better than other mentioned algorithms and it can be an effective approach for the automatic design of the analog CMOS circuits.

Carbon Nanotube CMOS Analog Circuitry

Carbon nanotube (CNT) field-effect transistors (CNFETs) promise significant energy efficiency benefits versus today's silicon-based FETs. Yet despite this promise, complementary (CMOS) CNFET analog circuitry has never been experimentally demonstrated. Here we show the first reported demonstration of full CNFET CMOS analog circuits. For characterization, we fabricate analog building block circuits: multiple instances of two-stage op-amps. These CNFET CMOS op-amps achieve gain >700 (maximum derivative of output voltage with respect to differential input voltage), operate at a scaled sub-500 mV supply voltage, achieve high linearity (even when operating at these scaled voltages), and are robust over time (minimal drift over >10 000 cycled measurements over 12 h). Additionally, we demonstrate a front-end analog subsystem that integrates a CNFET-based breath sensor with an analog sensor interface circuit (transimpedance amplifier followed by a voltage follower to convert resistance change of the chemoresistive CNFET sensor into a buffered output voltage). These experimental demonstrations are the first reports of the CNFET CMOS analog functionality that is essential for a future CNT CMOS technology.

Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems

In this paper, modeling of performance parameters and time efficient yet accurate sizing methodology of CMOS analog non-linear circuits have been proposed. The proposed modeling methodology generates empirical models of the non-linear circuit performance parameters in monomial or posynomial form, which is geometric programming (GP) compatible, as a function of the final design variables of the circuit (i.e. the width and length of the transistors). The proposed non-linear circuit sizing methodology, referred to as iterative geometric programming utilizes a correction factor for each of the GP compatible performance parameter models. These correction factors are updated using SPICE simulation after every iteration of the GP optimization. The proposed methodology takes advantage of GP optimization and at the same time it uses SPICE simulation to improve the design point by rectifying inaccuracies that may exists in the GP compatible performance models. Both the proposed methodologies have been validated in a 0.18 μm CMOS technology. The dynamic comparator and the bootstrap switch which are commonly used non-linear circuits in analog-mixed signal systems, have been used as the example circuits. It has been observed that the proposed sizing algorithm converges rapidly and give final design point with SPICE level accuracy higher than 99 %. The efficiency and the accuracy of the proposed algorithm has been numerically compared w.r.t. the sizing algorithm using evolutionary algorithm. It has been observed that the proposed algorithm gives much better results. Moreover, the proposed algorithm is hundreds times faster than that of the evolutionary algorithm.

Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks

We propose an innovative stochastic-based computing architecture to implement low-power and robust artificial neural network (S-ANN) with both magnetic tunneling junction (MTJ) and Domain Wall (DW) devices. Our mixed-model HSPICE simulation results have shown that, for a well-known pattern recognition task, a 34-neuron S-ANN implementation achieves more than 1.5 orders of magnitude lower energy consumption and 2.5 orders of magnitude less hidden layer chip area, when compared with its deterministic-based ANN counterparts which are implemented with digital and analog CMOS circuits. We believe that our S-ANN architecture achieves such a remarkable performance gain by leveraging two key ideas. First, because all neural signals are encoded as random bit streams, the standard weighted-sum synapses can be accomplished by stochastic bit writing and reading procedure. Second, we designed and implemented a novel multiple-phase pumping circuit structure to effectively realize the soft-limiting neural transfer function that is essential to improve the overall ANN capability and reduce its network complexity.

Time-dependent dielectric breakdown (TDDB) reliability analysis of CMOS analog and radio frequency (RF) circuits

In this paper, a methodology to analyze the time dependent dielectric breakdown (TDDB) reliability of CMOS analog and radio frequency (RF) circuits has been proposed and applied to common circuit b...