CMOS Adder Research Articles

Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration

Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this balance, significantly improving the performance of digital systems. Here, a 5-bit adder with a unique configuration is used in place of a Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA). Using CMOS & TG Configuration, all other internal structures have been created. Performance comparisons of the CMOS and TG 5-bit Adders with the adders above are shown in terms of power, latency, and area. Various adders: 5-bit Adder with CMOS & TG design, the CMOS & TG based CLA, the CSA, and the RCA, are also involved in the multiplier's adder unit selection process. The new multiplier provides the perfect answer for energy-efficient designs by combining low power consumption with small size.

Area and power delay product efficient level restored hybrid full adder (LR-HFA)

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

Probabilistic based CMOS Adder for High Speed Communication Systems

Power efficient is an important availability for various mobile devices and communication system applications. The proposed probabilistic adder is to trade a lesser amount of accuracy with reduced power dissipation. In this paper, the probabilistic adder is eliminating the some part of the carry propagation path in least significant bit to reduce the power consumption and transistor count. The power consumption and probabilistic error behaviour of the proposed adder is designed and compared with other adders.

On Approach to Optimize Manufacturing of a Single-Bit CMOS Adders Based on Heterostructures to Increase Integration Rate of Their Elements

On Approach to Optimize Manufacturing of a Single-Bit CMOS Adders Based on Heterostructures to Increase Integration Rate of Their Elements

On Optimization of Manufacturing of a Single-Bit CMOS Adder Based on Heterostructures to Increase Density of Their Elements. Influence of Miss-Match Induced Stress and Porosity of Materials on Technological Process

On Optimization of Manufacturing of a Single-Bit CMOS Adder Based on Heterostructures to Increase Density of Their Elements. Influence of Miss-Match Induced Stress and Porosity of Materials on Technological Process

Design and analysis of 32 bit CMOS adder using sub-threshold voltage at deep submicron technology

FA is basic cell for arithmetic operation and lots of efforts have put to minimize power consumption and delay. This paper evaluates conventional CMOS adder, bridge style adders in sub-threshold region. Circuits are designed at 20 MHz and 50 MHz frequencies with VDD= 200 mv. All adder designs are simulated at 32 nm technology. In 1 bit and 32 bit conventional CMOS adder design, an efficient trade-off between delay and power is achieved. Experimental results show that 32 bit adder designs have significant improvements in delay and power delay product.

A Comparative Study of High Speed CMOS Adders using Microwind and FPGA

In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.

Transmission Gate base Programmable Binary Incrementer Decrementer

We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle. For this, design of a faster and highly reliable adder is of major importance. Thus, much effort has been invested in the research that has led to faster and more efficient ways to perform this operation. To prove the efficiency of the proposed method, the circuit is simulated in pass transistor CMOS 50nm technology and some simulation parameters are calcultes in the layout of the circuit. The binary decrementer reduces the stored binary data in memopry or register by ‘1’. This can be done by using 2’s complement method by using XOR gates which convert binary data in 1’s complement and then by addition of binary ‘1’ it can be converted to 2’s complement form. It is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded half adder circuits. This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.

Comparative analysis of CMOS adders circuits based on 10 transistors

Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out.

Low-power high-sensitivity spike detectors for implantable VLSI neural recording microsystems

A spike detector has become a necessity of a contemporary multichannel neural recording microsystem for data-compression. This paper proposes two spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity degradation suffered by the conventional nonlinear energy operator (NEO) at the presence of large-amplitude baseline interferences. The efficiency of NEO, fNEO and ED algorithms are evaluated with Simulink programs firstly and then implemented into three low-power spike detectors with a standard 0.13- $$\mu m$$ μ m CMOS process. To achieve a low-power design, subthreshold CMOS analog multipliers, derivatives and adders are developed to work with a low supply voltage, 0.5 V. The power dissipation of the proposed fNEO spike detector and ED spike detector are only 258.7 and 129.4 nW, respectively. The quantitative investigation shown in the paper indicates that both fNEO and ED spike detectors achieves superior performance than the conventional NEO spike detector. Considering its lowest power dissipation, the ED spike detector is selected for our application. Further statistical evaluations based on the true positive and false positive detection rate proves that the ED spike detectors achieves higher detection rate than that of the conventional NEO spike detector but dissipates 48 % less power.

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

Low-power, compact, and high-performance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nanotube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53%, 77.96%, and 15.52% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54%, 95.57%, and 25.66% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the other adder circuits that are evaluated in this study.

Study of Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates

Full adders are vital components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor FA using novel XOR and XNOR gates in combination with existing ones.We have done over ten thousand HSPICE simulation runs of the entire the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while 3 new adders consistently use on average 10% less power and have higher speed compared with the previous Ten-transistor full adder and the conventional 28-T CMOS adder. One draw back of the novel adders is the threshold-voltage loss of the pass transistors.

A circuit implementation of a single-bit CMOS adder

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.

Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool

In this Research Paper, the focus is on the analysis and simulation of the Adder cell which is slightly different as compared to the existing circuits and optimized for Average Power Dissipation. In this paper the adder cell is modified circuit in such a way that it controls the overall capacitances during the Sum and Carry evaluation and will optimize the total capacitance that results in the decrease of the Average Power dissipation. The circuit is characterized by using HSPICE in a 180 nanometer (nm) with supply voltage of 1.8 volt and threshold voltage is 0.40 volts.

Systematic Analysis on Power Consumption in Conventional Cmos, Multiplexer Based and Hybrid Adder

There has been a rapid increase in the popularity of portable and wireless electronic devices, like laptop computers, portable video players cellular phones, which rely on embedded digital signal processors. Since the desire is to design digital systems at best performance without power sacrifices, the need for high performance and low power multipliers is inevitable. Since multiplication is one of the most critical operations in many computational systems, Multipliers are in fact complex adder arrays. In this paper we performed a comparative analysis on power consumption in three different adders, each offering different advantages and having tradeoffs in terms of circuit complexity and power consumption. The 28 Transistor full adder is the pioneer CMOS traditional adder circuit. Which is the one which consume more power when compare to other two adder, the number of transistors required for conventional CMOS adder is 28. Recently, it has been proved that the multiplexer-based multiplier outperforms the modified Booth multiplier both in speed and power dissipation by 13% to 26%, due to small internal capacitance. After analyzing the performance characteristics of conventional multiplier types, it is observed that the one designed using multiplexer-based multiplication algorithm is more advantageous, especially when the size of the multiplied numbers is small. The number of transistors required for multiplexer based adder is 16. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. The hybrid adder models which consume low power among all three adder and the number of transistors required is 12. As an added advantage there will be no path from one voltage level (VDD) to the other (GND).The elimination of the direct path to the ground removes the short circuit power component for the adder module. This reduces the total energy consumed in the circuit and making it an energy efficient design. The SERF adder is not only energy efficient but also area efficient due to its low transistor count.

Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM

This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony with the trend shown in transistor adders.

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

This paper presents a comparative study of high‐speed and low‐voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR‐XNOR (3T) design style is discussed. This paper also discusses a high‐speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low‐power Majority‐function‐based 1‐bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single‐ended supply voltage, and simulations are carried out on Spectre S.

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.