Closed-loop Amplifier Research Articles

A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS

In this paper, we propose a merge-mismatch-error-shaping (M-MES) noise shaping SAR ADC as a solution to address the limitation of SNDR caused by the non-linearity resulting from DAC mismatch. The proposed M-MES technique is based on MES with the introduction of capacitive merging to mitigate the degradation of dynamic range (DR) in ADCs. In addition, to meet the high signal-to-noise ratio (SNR) and low power requirements of the ADC, cascaded integrator feed-forward (CIFF) noise shaping ADC in this paper is a first-order filter based on a closed-loop amplifier. The proposed ADC was simulated and designed in a 180-nm CMOS process, which consumes 449 μW of power when operating at 1 MS/s sampling frequency. According to the post-simulation results, under a 3.3-V supply and at an oversampling ratio (OSR) of 500, the proposed ADC achieves Schreier FoMS of 168.5 dB with 102.1 dB signal to noise and distortion ratio (SNDR) and 102.2 dB spurious free dynamic range (SFDR).

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.

This article presents a low-noise high-power-efficiency analog front-end (AFE) for capacitive-micromachined-ultrasonic transducers (CMUT). Implemented in 28-nm CMOS technology, the proposed AFE features three-stage continuous time-gain compensation (TGC) embedded in both trans-impedance amplifiers (TIAs) and an analog beamformer to provide a large compensation range with no extra power-consumption cost. The use of noise cancellation and capacitive feedback optimizes the noise performance of TIAs. The first stage of the TGC is built in the TIA by adjusting the positive and negative resistance loads, which are composed of voltage-controlled transistor arrays. An all-pass passive network is used as the delay unit of the analog beamformer, meanwhile achieving the second TGC stage. Phase shift for all frequency components in the ultrasound pass-band is manifested as a delay to the echoes. The third stage of the TGC is merged with a summing unit, which is a closed-loop amplifier with variable resistance feedback. The design takes into account the ability to handle large signals and power consumption, with TIA and beamforming operating at voltages of 2.5 V and 0.9 V, respectively. Experimental results show that the proposed AFE achieves a 2.11 pA/√Hz input-referred noise (IRN) at the 5 MHz center frequency of the echoes while consuming only 1.02 mW/channel. A total exponential TGC range of 60 dB with continuous ranges of 12 dB, 24 dB, and 24 dB assigned to three stages has been verified for this work.

A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of −109.1 dB and can deliver a maximum of 14 W into an 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 93% efficiency while occupying a silicon area of 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A High Dynamic Range Vibration Radar Sensor With Automatic DC Voltage Extraction

One challenge of using a homodyne receiver to obtain accurate vibration information is the undesired DC voltage in a continuous wave radar. It reduces the output dynamic range and even saturates the signal path. In this paper, an adaptive DC extraction method with flexible clocks is proposed in a 5.8 GHz Doppler radar to separate the DC component from the input signal. Rather than simply eliminating the DC component, the proposed method digitizes the DC component as well as the input AC signal with a large dynamic range. It is accomplished by a mixed-signal feedback loop and features an excellent accommodation to large input DC variations and flexible settling time. In the loop, a closed-loop amplifier is used as the input stage and an ADC is followed to digitize the amplified quadrature signals from the radar. Afterward, a simplified digital filter is cascaded to extract the digital version of the DC component and feedback to the input stage. In this way, both the DC component and AC component in the input signal are separated and digitized without saturation. For verification, several simulations and experiments were conducted. The results show that a wide DC range can be tolerated and extracted. What&#x2019;s more, the target motion with sub-millimeter amplitude can be successfully captured based on the proposed DC extraction loop.

A 120-MHz Broadband Differential Linear Driver With Channel Mismatch Cancellation and Bandwidth Extension for B-PLC Applications

This paper introduces a broadband linear driver used in B-PLC system. The driver consists of two identical current-feedback amplifiers to realize a fully differential topology. A cross-current injection method between the noninverting and the inverting channels is proposed to reduce the even-order harmonics caused by the circuit mismatch. In addition, in order to increase the stability of the GBW to the changing load and maximize the bandwidth, a output stage implemented by a unit gain closed-loop amplifier is proposed to stabilize the open-loop gain of the overall circuit, meanwhile improve the linearity deteriorated by the crossover distortion. The proposed linear driver is fabricated in a SOI CBJT process and it can provide a maximum drive current of 500 mA under a 12-V power supply. The measurement results show that this linear driver is capable of driving a load of <inline-formula> <tex-math notation="LaTeX">$50~\Omega $ </tex-math></inline-formula> while achieving a output swing of <inline-formula> <tex-math notation="LaTeX">$16~{V_{pp}}$ </tex-math></inline-formula> with a second-order harmonic distortion (HD₂) of &#x2212;72 dBm and a third-order harmonic distortion (HD₃) of &#x2212;55 dBm. The bandwidth can reach 120 MHz. A complete in-system measurement also has been passed and the results show that the proposed driver chip can well meet the need of the B-PLC system.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques

This article presents a discrete-time second-order $\Delta \Sigma $ modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm2 core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49- $\mu \text{W}$ power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60°. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.

A new fast settling low power CMOS gain stage architecture

This paper presents a new gain stage for high accuracy and fast settling applications. In the proposed structure a novel combination of closed loop and open loop amplifiers is employed to achieve high accuracy and enhanced settling behavior while adding only negligible power to the main circuit power constraint. To evaluate the functionality of the proposed idea, a zero cross based circuit and a switch capacitor amplifier are designed to implement the open loop and the closed loop stages, respectively. Though, other topologies for implementation of open loop and closed loop amplifiers are applicable in the presented gain stage. The proposed structure is implemented in 0.18 μm CMOS technology. HSPICE simulation results, using level 49 models, demonstrate that the new configuration improves the power efficiency and the settling behavior as well as the system accuracy. The proposed scheme shows very fast settling times of 0.8, 1.01, 1.41 ns for the gain accuracies of 6, 8 and 10 bits, respectively, while loaded with 1 pF capacitance and the output swing is 1.6 V. In comparison with a conventional switched capacitor closed loop amplifier, the proposed architecture improves the settling performance by a factor of 3 for 6 bit resolution, while it adds only 0.63 mW power to the total power consumption that is 8.68 mW.

Enhancement of Closed-Loop Gain of Organic Amplifiers Using Double Gate Structures

We demonstrate a significant improvement in the gain of closed-loop organic amplifiers by systematically controlling the threshold voltage ( $V_{\mathrm {TH}})$ with double-gate structures. The use of an ultrathin parylene dielectric results in an operating voltage as low as 4 V with a supply voltage ( $V_{\mathrm {DD}})$ of 2 V. Double-gate structures were introduced for controlling $V_{\mathrm {TH}}$ of the transistor and the switching voltage of the inverter. The maximum dc gain of the inverter was recorded as 29.3 dB at a $V_{\mathrm {DD}}$ value of 2 V. In addition, the switching voltage of the circuits can be controlled from 0 V to $V_{\mathrm {DD}}$ without a significant performance degradation. The effects of the $V_{\mathrm {TH}}$ control on the closed-loop amplifier were systematically investigated and a significant gain improvement of up to 18.8 dB was demonstrated in the closed-loop gain by adjusting the switching voltage to half of $V_{\mathrm {DD}}$ .

Highly Matched TO Pseudo-resistors for Multi-channel Neural Signal Recording Applications

Event Abstract Back to Event Highly Matched TΩ Pseudo-resistors for Multi-channel Neural Signal Recording Applications Vijay Viswam1*, Yihui Chen2, Raziyeh Bounik2, Amir Shadmani1, Jelena Dragas2, Jan Müller2 and Andreas Hierlemann2 1 ETH Zürich, Department of Biosystems Science and Engineering, Switzerland 2 ETH Zurich, Department of Biosystems Science and Engineering, Switzerland Motivation To reduce drift and offset of electrodes, neural amplifiers usually employ high pass filters with very low corner frequencies (e.g., fHPF<10Hz). This approach requires huge on-chip resistances (~T½). To keep the silicon area small, "pseudo-resistors" (MOS transistors biased in the weak inversion region) are frequently used [1], but their resistance may considerably vary due to processing and fabrication spread, temperature fluctuations, and even different locations on the same chip may feature different properties. Here, specific new pseudo-resistor structures have been devised to achieve small fHPF variations. Material and Methods The new pseudo-resistors were implemented in a CMOS high-density MEA system incorporating 2048 readout channels [2]. Two different kinds of pseudo-resistor topologies were devised. For the 1st stage, open-loop amplifiers were used, while, for the 2nd stage closed-loop amplifiers were implemented. Aided by the current mirrors and level shifters, the first-order dependence of the overdrive voltages of the transistors inside RPR1 and RPR2 on their threshold voltages was cancelled out. Thus, RPR1 and RPR2 variations were substantially reduced, which lead to small fHPF variations. A wide range of resistances could also be realized by changing the bias currents, which could be digitally tuned with 7-bit current DACs implemented on-chip. Results High pass filter corner frequency (fHPF) of the the neural amplifiers tuned by pseudo-resistors were measured. The uniformity of fHPF showed the inter-channel matching of pseudo resistors across 2048 channels in the high and low frequency range. Conclusions Current-biased pseudo-resistors for neural signal recording applications are introduced in this work. The two new structures enable to realize very large resistances while keeping the silicon area small. Results on the transfer function of the neural amplifiers and the matching of the pseudo-resistors have been shown in this paper. The circuits were fabricated in 180nm 6M1P CMOS technology.

A Low-THD Class-D Audio Amplifier With Dual-Level Dual-Phase Carrier Pulsewidth Modulation

In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulsewidth modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180° out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of $\pm$ 5 V.

A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\Sigma\Delta$&lt;/tex&gt; &lt;/formula&gt; ADC for a Digital Closed-Loop Class-D Amplifier

This paper presents a continuous-time third-order ΣΔ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed ΣΔ modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.

A 55-dB SNDR, 2.2-mW double chopper-stabilized analog front-end for a thermopile sensor

A double chopper-stabilized analog front-end (DCS-AFE) circuit for a thermopile sensor is presented, which includes a closed-loop front-end amplifier and a 2nd-order 1 bit quantization sigma—delta modulator. The amplifier with a closed-loop structure ensures the gain stability against the temperature. Moreover, by adopting the chopper-stabilized technique both for the amplifier and 2nd-order 1-bit quantization sigma—delta modulator, the low-frequency 1/f noise and offset is reduced and high resolution is achieved. The AFE is implemented in the SMIC 0.18 μm 1P6M CMOS process. The measurement results show that in a 3.3 V power supply, 1 Hz input frequency and 3KHz clock frequency, the peak signal-to-noise and distortion ratio (SNDR) is 55.4 dB, the effective number of bits (ENOB) is 8.92 bit, and in the range of −20 to 85 degrees, the detection resolution is 0.2 degree.

Low-Noise Front-End Receiver Dedicated to Biomedical Devices: NIRS Acquisition System

This paper concerns the design and the implementation of a fully integrated front-end intended to Near-Infrared Spectroscopy System (NIRS) acquisition system. A low-noise transimpedance amplification (TIA) circuit followed by adjustable cut-off frequency and a low-pass filter (LPF) was implemented in order to decrease noise circuit of NIRS detectors. For TIA, a single ended common source, common gate input stage based on a cascode structure is used to get a higher gain-bandwidth closed-loop transimpedance amplifier. To enhance the circuit noise performance, a single feedback transistor technique is used, compared to passive feedback, to achieved high quality data from NIRS acquisition channel. The proposed LPF combines two control methods to adjust the low cut-off frequency. Simulation results show a TIA gain of 104.2 dBΩ, ?3dB bandwidth of 19 MHz and an equivalent input noise current spectral density of 446 fA/√Hz. LPF filter exhibits a relatively constant noise 201nV/√HzQUOTE√Hz from 0 Hz to 700 KHz and linearity performance over its entire tuning range. The proposed front-end of NIRS preamplifier is implemented using 0.18 μm CMOS technology.

Design of Ultra-Low Power Biopotential Amplifiers for Biosignal Acquisition Applications

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

Time-Domain Analysis of Intermodulation Distortion of Closed-Loop Class-D Amplifiers

This paper presents a time-domain analysis of the intermodulation distortion (IMD) of a closed-loop Class-D amplifier (amp) with either first- or second-order loop filter. The derived expression for the IMD indicates that there exist significant third-order intermodulation products (3rd-IMPs) within the output spectrum, which may lead to even greater distortion than the intrinsic harmonic components. In addition, the output expressions are compact, precise, and suitable for hand calculation so that the parametric relationships between the IMD and the magnitude and frequency of the input signals, as well as the effect of the loop filter design are straightforwardly investigated. In order to accurately represent the IMD performance of class-D amp, a modified testing setup is introduced to account for the dominantly large 3rd-IMPs when the International Telecommunication Union Radiocommunication Sector (ITU-R) standard is applied.

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed-loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed-loop bandwidth is kept ideally constant irrespective of the closed-loop gain. The proposed method can be applied to any amplifier adopting dominant-pole compensation. As an example, we designed a CMOS amplifier providing 66-dB direct current gain and 310-MHz gain-bandwidth product. For closed-loop gains ranging from 1 to 10, the closed-loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed-loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.

Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators

This paper presents an integrated stereo audio amplifier that employs sigma---delta (ΣΔ) modulation techniques with compensators. Traditional closed-loop audio amplifiers adopt pulse-width modulation or ΣΔ modulation techniques. The design method proposed in this study uses a negative feedback closed-loop system with compensator and ΣΔ modulator. This combination of compensator and ΣΔ modulator significantly reduces the noise and total harmonic distortion (THD) compared with a traditional closed-loop system. The proposed negative feedback loop can automatically compensate for external perturbations, improving the precision of the eventual output. The compensator increases the audio-frequency loop gain, and leads to better rejection of audio-frequency disturbances. At a sample rate of 10 MHz, the proposed audio amplifier achieves 0.04% THD and a signal to noise ratio of 87 dB with efficiency above 92%. The proposed audio amplifier was implemented in a TSMC 3.3 V 0.35 μm 2P4M CMOS process.

Modelling of Digital Assisted Backend Correction Analogue to Digital Converters with Verilog-A

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.