A new fast settling low power CMOS gain stage architecture

Abstract

This paper presents a new gain stage for high accuracy and fast settling applications. In the proposed structure a novel combination of closed loop and open loop amplifiers is employed to achieve high accuracy and enhanced settling behavior while adding only negligible power to the main circuit power constraint. To evaluate the functionality of the proposed idea, a zero cross based circuit and a switch capacitor amplifier are designed to implement the open loop and the closed loop stages, respectively. Though, other topologies for implementation of open loop and closed loop amplifiers are applicable in the presented gain stage. The proposed structure is implemented in 0.18 μm CMOS technology. HSPICE simulation results, using level 49 models, demonstrate that the new configuration improves the power efficiency and the settling behavior as well as the system accuracy. The proposed scheme shows very fast settling times of 0.8, 1.01, 1.41 ns for the gain accuracies of 6, 8 and 10 bits, respectively, while loaded with 1 pF capacitance and the output swing is 1.6 V. In comparison with a conventional switched capacitor closed loop amplifier, the proposed architecture improves the settling performance by a factor of 3 for 6 bit resolution, while it adds only 0.63 mW power to the total power consumption that is 8.68 mW.