Clock Zones Research Articles

확장성을 고려한 QCA XOR 게이트 설계

CMOS (complementary metal-oxide-semiconductor)의 소형화에 대한 한계를 극복할 수 있는 대체 기술 중 하나인 양자 셀룰라 오토마타 (QCA; quantum cellular automata)는 나노 단위의 셀들로 이루어져 있고, 전력의 소모량이 매우 적은 것이 특징이다. QCA를 이용한 다양한 회로들이 연구되고 있고, 그 중에서 XOR (exclusive-OR)게이트는 오류 검사 및 복구에 유용하게 사용되고 있다. 기존의 XOR 논리 게이트는 확장성이 부족하고, 클럭 구간의 수가 많이 소요되며, 실제 구현에 어려움이 있는 경우가 많다. 이러한 단점을 극복하기 위해 클럭 구간의 수를 단축한 다수결 게이트를 이용한 XOR 논리 게이트를 제안한다. 제안한 회로는 기존의 XOR 논리 게이트들과 비교 분석하고 그 성능을 검증한다. Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.

Modular Design of 2 n :1 Quantum Dot Cellular Automata Multiplexers and its Application, via Clock Zone based Crossover

Modular Design of 2 n :1 Quantum Dot Cellular Automata Multiplexers and its Application, via Clock Zone based Crossover

On the reliability of majority logic structure in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is projected to be a promising nanotechnology due to its extremely small feature size and ultra low power consumption. However, acceptance of a QCA design is limited due to its high defect rate. Efficient fault tolerant schemes are, therefore, needed for reliable design. This work targets design of a new fault tolerant scheme around QCA logic primitives which encapsulates two different orientations of QCA cell. A 2×2 array of four rotated (‘+’) cells, called complementary tile (CT), is introduced to maximize the throughput. It ensures 100% fault tolerance under single cell missing defect. Two reliable majority voters (RMV), based on the CT, are designed which outperforms the existing majority logic in QCA. The functional characterization and polarization of RMV under different cell deposition (missing/additional) defects are covered. The significance of the clocking in fault tolerance is also investigated with RMV with multi clock zone. The error probability model for the proposed RMV, under cell deposition (missing/additional) defect, is developed to ensure better understanding of reliability in QCA.

Towards the hierarchical design of multilayer QCA logic circuit

As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01μm2) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches.

Combinational Circuit Design Based on Quantum-Dot Cellular Automata

Quantum-dot cellular automata(QCA) provides a new approach in computer circuit design and development at nanotechnology level. This technology promises extraordinary high computing speeds, low heat dissipation and highly dense circuits. In this paper,two 2:4 decodersare proposed. The proposed structures reduce the clock phases to only three phases making them faster than the designs currently available in literature.The first proposed structure has reduced number of cells and hence covers a small area.The second proposed method although it has more cells, has regular clock zones that can facilitate the implementation of this circuit.Simulation of the circuits was done using QCADesigner.

Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCADesigner, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show 23% cell count and 48% area improvements over the best previous QCA full adder design. Similar results for 4-, 8-, 16-, 32-, and 64-bit adders are 29% (22%), 24% (51%), 19% (54%), 13% (69%), and 9% (49%) cell count reduction (less area consumption), respectively.

Reversible Binary to Grey and Grey to Binary Code Converter using QCA

ABSTRACTQuantum dot-cellular automata (QCA) is an emerging nanotechnological archetype and has widespread applications in designing nanoscale reversible circuit for nanocomputing. The low power consumption, faster operating speed, and low circuit area of QCA pledge the energy efficient design of logic circuit having high device complexity. This paper demonstrates the design of reversible binary to grey and grey to binary code converter based on Feynman gate using QCA for the first time. Both the proposed reversible code converter circuits have quantum cost as 2. The conversion of binary to grey code is achieved with only one garbage value and the grey to binary code conversion is achieved without any garbage value. The proposed Feynman gate circuit required only 38,880 nm2 areas and three clocking zones. The reversible binary to grey circuit required only 92,664 nm2 areas and three clocking zones whereas the reversible grey to binary circuit required only 139,968 nm2 areas and four clocking zones. The proposed design can be used to realise the nanoarchitecture in computer communication having low power consumption. The evaluation of simulation outcomes of proposed circuit with theoretical knowledge established the functional efficiency of the circuits. The circuits are designed and simulated by QCA Designer-2.0.3.

Contiguous clock lines for pipelined nanomagnet logic

In this paper we study pipelined nanomagnet logic by simulating and comparing varying adjacent clock line structures. Unlike previous simulations, a realistic clock line shape is used in simulations to obtain a more accurate idea of whether or not these clock lines function properly. First, we simulate individual clock lines using Ansys Maxwell 2D according to the parameters of the fabricated clock lines. Then, these clock lines are placed adjacent to one another to simulate how data can propagate from one clock zone to another. Adjusting the clock line layer structure minimizes a dip in the magnetic field at the clock zone boundaries from 35% minimum below the clocking field to a 16% dip. These magnetic field profiles are then used in the object-oriented micromagnetic framework (OOMMF) to simulate lines of nanomagnets. By reducing the gap between contiguous clock lines, we show error free data propagation in the form of a ferromagnetically coupled line of nanomagnets.

Design of Efficient Full Adder in Quantum‐Dot Cellular Automata

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture

Dipolar magnetic coupling between single layer nanomagnets is used in nanomagnetic logic (NML). Apart from writing and reading, nanomagnets are also clocked using external magnetic fields generated by current carrying wires. The related current ranges in mA and consumes large power. Also, the fields cannot sharply terminate at boundaries between nanomagnets that are required to be in different clock zones. The above concerns motivated us to look into alternate magnetic devices to realize magnetic logic. We therefore suggested miltilayer magnetic tunnel junctions (MTJs) for logic. We have observed that MTJ free layers can interact with their neighbors through magnetic coupling. In this paper we have proposed use of this coupling for effective logic computation. MTJs are also CMOS friendly, a property that we used to write, clock and read from logic. CMOS integration also improves control over individual elements in logic. In this paper we have used these properties to present a novel CMOS-MTJ integrated architecture that: a) computes logic using magnetic coupling between MTJs and b) writes, clocks and reads from logic using spin transfer torque (STT) current that is more energy efficient. A feasibility study of this CMOS-MTJ integration in 22 nm CMOS technology node is also presented. The proposed architecture achieves an energy reduction >;95% in adders and multipliers when compared to traditional designs using single layer nanomagnets.

Сomputer simulation of nanoelectronics arithmetic-logic devices

This paper presents a quantum dot cellular automata two bit multiplier composed from simple 3-input majority gates and inverters. It is reviewed two different methods of conductors crossing and specifics of QCA devices construction correspondently. The way of device working area partition onto clocking zones is defined. Also it is defined the latency of designed multiplier. Research focuses on the design and simulation of QCA using numerical tools such as the QCADesigner tool.

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

SUMMARYQuantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.

Design of quantum-dot cellular automata circuits using cut-set retiming

As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCA's unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCA's unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.

Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata

Quantum Cellular Automata (QCA) is a novel and attractive method which enables designing and implementing high-performance and low-power consumption digital circuits at nano-scale. Since memory is one of the most applicable basic units in digital circuits, having a fast and optimized QCA-based memory cell is remarkable. Although there are some QCA structures for a memory cell in the literature, however, QCA characteristics may be used in designing a more optimized memory cell than blindly modeling CMOS logics in QCA. In this paper, two improved structures have been proposed for a loop-based Random Access Memory (RAM) cell. In the proposed methods, the inherent capabilities of QCA, such as the programmability of majority gate and the clocking mechanism have been considered. The first proposed method enjoys smaller number of cells and the wasted area has been reduced compared to traditional loop-based RAM cell. For the second proposed method, the memory access time has been duplicated in presence of smaller number of cells. Irregular placement of QCA cells in a QCA layout makes its realization troublesome. So, we have proposed alternative versions of the proposed methods that exploit regularity of clock zones in design and have compared them to each other. QCA designer has been employed for simulation of the proposed designs and proving their validity.

Iris Pattern Positioning with Preserved Edge Detector and Overlay Matching

An iris image pattern positioning with preserved edge detector, ring zone and clock zone, frequency distribution and overlay matching is presented in this paper. Edge detector is required to be powerful and detail. That is proposed by overlaying Canny with LOG (CLOG). The two reference patterns are made from allocating each gray level on the clock zone and ring zone respectively. The normalized target image is overlaid with the clock zone reference pattern and the ring zone pattern to extract overlapped number, and make a matched frequency distribution to look through a symptom and position of human organ and tissue. The iterating experiments result in the ring and clock zone positioning evaluation.

Low power dual-edge triggered flip-flop structure in quantum dot cellular automata

Artificial molecule quantum dot cells are a promising currentless nanotechnology, which can be used for realising fully digital circuits and systems. A dual-edge triggered module and flip-flop sequential circuit are proposed using quantum dot cellular automata (QCA) cells by arranging special clock zones subtly and serially. A D flip-flip case is given to show how a low power dual-edge triggered flip-flop can be realised using quantum dot cell arrays. The proposed structure is promising in building future nanoscale ultra low power information processing systems and may inspire higher clock speed applications in QCA.

Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology, with extremely small feature size and ultralow power consumption comparing with transistor-based technology. Anteriority, basic level-triggered flip-flop designs based on QCA implementation were examined. In this paper, we utilize the unique QCA characteristics and clock zones to design falling edge-triggered J-K flip-flop that is stable and practical. Simulation with the QCADesigner simulator is performed to verify the functionality of the proposed falling edge-triggered flip-flop. This paper also explores the design of counters. Synchronous counters are designed with several different bit sizes and simulation results demonstrate the validity of them.

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking

This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the QCADesigner simulator are performed to verify the functionality of the proposed QCA memory cell.

Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits

The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a collection of QCA cells, each with two possible ground states. A four-phased clocking scheme has been suggested to keep the computations at the ground state throughout the circuit. This clocking scheme, however, induces latency or delay in the transmission of information from input to output. In this paper, we study the interplay of computing error behavior with delay or latency of computation induced by the clocking scheme. Computing errors in QCA circuits can arise due to the failure of the clocking scheme to switch portions of the circuit to the ground state with change in input. Some of these non-ground states will result in output errors and some will not. The larger the size of each clocking zone, i.e., the greater the number of cells in each zone, the more the probability of computing errors. However, larger clocking zones imply faster propagation of information from input to output, i.e., reduced delay. Current QCA simulators compute just the ground state configuration of a QCA arrangement. In this paper, we offer an efficient method to compute the N-lowest energy modes of a clocked QCA circuit. We model the QCA cell arrangement in each zone using a graph-based probabilistic model, which is then transformed into a Markov tree structure defined over subsets of QCA cells. This tree structure allows us to compute the N-lowest energy configurations in an efficient manner by local message passing. We analyze the complexity of the model and show it to be polynomial in terms of the number of cells, assuming a finite neighborhood of influence for each QCA cell, which is usually the case. The overall low-energy spectrum of multiple clocking zones is constructed by concatenating the low-energy spectra of the individual clocking zones. We demonstrate how the model can be used to study the tradeoff between switching errors and clocking zones.

A Serial Memory by Quantum-Dot Cellular Automata (QCA)

Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nanotechnology. QCA systems require extremely low power, together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line of a clocking zone is independent of the word size. QCA circuits for address decoding and input/output for simplification of the Read/Write operations are discussed in detail. An extensive comparison of the proposed architecture and previous QCA serial memories is pursued in terms of latency, timing, clocking requirements, and hardware complexity.