Сomputer simulation of nanoelectronics arithmetic-logic devices

Abstract

This paper presents a quantum dot cellular automata two bit multiplier composed from simple 3-input majority gates and inverters. It is reviewed two different methods of conductors crossing and specifics of QCA devices construction correspondently. The way of device working area partition onto clocking zones is defined. Also it is defined the latency of designed multiplier. Research focuses on the design and simulation of QCA using numerical tools such as the QCADesigner tool.