Abstract
Adders and Subtractors are an integral part of every digital information processing system. In general, it is always preferred to have a unified hardware that can perform both operations to reduce the area of circuits. The transistor technology is facing several difficulties to cope up with the targets set by Moore’s law. Researchers have started to focus on finding alternatives. Quantum-dot Cellular Automata nanotechnology is suggested by the researchers for circuit design at nanoscale levels. A full adder-subtractor circuit using clock zone and multilayer crossover are proposed in this work. The results show that they have minimal cells and area. The fault tolerance capacity of the designs to missing cell defects is also analyzed. The full adder-subtractor coplanar design is 86.7% fault resistant and the multilayer design is 76.5% fault resistant. The coherence vector simulation engine is used to perform all the simulations in QCA designer.
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