Clock Tree Topology Research Articles

Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces

Reliable timing verification is a primary challenge in three-dimensional (3-D) integrated circuits. Process, temperature, and voltage variations between tiers within an integrated system introduce timing uncertainty into the clock and data paths, resulting in reduced operating speed. A clock tree topology that supports synchronous and source synchronous timing schemes is proposed for 3-D interfaces. The interface operates in a source synchronous scheme for fast data transfer and transitions to a synchronous scheme for bidirectional data flow. Phase compensation for the synchronous scheme is achieved via a delay locked loop.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution

Clock power, skew and maximum latency are three key metrics for clock distribution in low-power and high-performance designs. An H-tree offers minimum clock skew and good robustness against variations, but at the cost of large wirelength and clock power. On the other hand, a “fishbone” clock network with spine-ribs structures has smaller wirelength, latency and clock power, but larger skew, as compared to an H-tree. No previous work enables systematic exploration of the regime between H-tree and spine to achieve an optimal tradeoff among clock power, skew, and latency. In this paper, we study the concept of a generalized H-tree (GH-tree)—a topologically balanced tree with an arbitrary sequence of branching factors—and propose a dynamic programming-based method to determine optimal clock power, skew, and latency, in the space of GH-tree solutions. Our method co-optimizes clock tree topology and buffering along branches according to fitted electrical models. We further propose a balanced ${K}$ -means clustering and a linear programming (LP)-guided buffer placement approach to embed the GH-tree with respect to a given sink placement. We validate our solutions in commercial clock tree synthesis (CTS) tool flows, in a commercial foundry’s 28LP technology. The results show up to 30% clock power reduction while achieving similar skew and maximum latency as CTS solutions from recent versions of leading commercial place-and-route tools. Our proposed approach also achieves up to 56% clock power reduction while achieving similar skew and maximum latency as compared to CTS solutions from a state-of-the-art academic tool.

Effect of process variations in 3D global clock distribution networks

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

Efficient implementation of a planar clock routing with the treatment of obstacles

This paper presents a set of techniques for developing a planar clock routing with the treatment of obstacles in high speed VLSI design. The planar clock routing framework has two key components. The first component employs a cutting-line embedding (CLE) routine algorithm to construct a planar clock tree topology. The routing constructed by CLE contains crossings over the obstacles in the presence of obstacles. Thus, the second component is a planar obstacle-avoiding (POA) routing scheme to clean up those crossings. These two schemes together give a good enhancement in convenient usage and performance to build a planar clock routing.

Synthesis of clock tree topologies to implement nonzero clock skew schedule

Designing the topology of a clock distribution network is considered for a synchronous digital integrated circuit so as to satisfy a nonzero clock skew schedule. A methodology and related algorithms for synthesising the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming problem. The approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to 64% performance improvement is attained on these circuits by exploiting nonzero clock skew throughout the synchronous system. Clock tree topologies that implement the nonzero clock skew schedule based on the synthesis algorithms presented are described for each of the benchmark circuits.

Zero skew clock routing with minimum wirelength

The deferred-merge embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength, is presented. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wire length reduction over some previous constructions. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. A unified BB+DME algorithm, which constructs a clock tree topology using a top-down balanced bipartition (BB) approach and then applies DME to that topology, is also presented. The experimental results indicate that both the topology generation and embedding components of the methodology are necessary for effective clock tree construction. >