Clock Signal Distribution Research Articles

Clock synchronizing radio access networks to picosecond precision using optical clock distribution and clock phase caching

Performing positioning of future mobile devices using trilateration through radio access networks would provide a robust alternative to currently used global navigation satellite systems. However, the positioning accuracy is strongly dependent on the time synchronization accuracy of the antennas used as location reference points. Consequently, achieving sub-30 cm positioning accuracies requires the synchronization of radio access network antennas to sub-nanosecond accuracy. Here we show a clock phase synchronization and optical clock signal distribution approach to clock synchronization in radio access networks that achieves 0.98-ps root-mean-square precision clock synchronization, in a real-time field-trial demonstration on 37.6-km dark fiber, with optical clock frequency synchronization and clock phase caching operating using 25.6-Gb/s commercial transceivers. We quantify the clock synchronization performance of our approach using standard metrics, including time deviation (TDEV) and mean time interval error (MTIE). Furthermore, we estimate the impact of varying the phase update rate used in clock phase caching on the clock synchronization performance of our approach. Through our two combined approaches, we explore a route towards achieving sub-nanosecond clock synchronization in radio access networks.

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

A clock distribution network (CDN) is a ubiquitous on-chip element that provides synchronized clock signals to all different circuit blocks in the chip. To maximize the chip performance, today’s CDN demands lower jitter, skew, and heat dissipation. Conventionally, on-chip clock signals have been distributed in the electric voltage domain, resulting in increased jitter, skew, and heat dissipation due to clock drivers. While low-jitter optical pulses have been locally injected in the chip, research on effective distribution of such high-quality clock signals has been relatively sparse. Here, we demonstrate femtosecond-precision distribution of electronic clocks using driver-less CDNs injected by photocurrent pulses extracted from an optical frequency comb source. Femtosecond-level on-chip jitter and skew can be achieved for gigahertz-rate clocking of CMOS chips by combining ultralow comb-jitter, multiple driver-less metal-meshes, and active skew control. This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.

Automated, adaptive, fast reset circuit for wide-energy range detector front-end

In this article, we present a front-end amplifier that is equipped with a precise, fast, and automated reset circuit responsible for two actions: restoring the charge-sensitive amplifier output voltage from a pulse level to baseline, and the analog-to-digital conversion of the pulse amplitude. Importantly, the circuit is self-clocking, which allows to take advantage of the modern submicrometer CMOS process, and thus speed-up the reset and conversion phases. Thanks to the proposed approach, the fast clock signal distribution and an independent analog-to-digital converter per channel are not required, saving both the power consumption and the silicon area. The presented circuitry was adopted into 100-pixel-shaped recording channels and sent for fabrication in the CMOS 28 nm process.

Clock signal distribution with second order nodes: Design hints

Despite being in use since the 1960’s, clock distribution networks continue to be important, mainly since the digitalization of numerous electronic tasks, which demands precise time measures for synchronizing internal and external processes in computational and instrumentation applications. Designing clock distribution networks requires determination/estimation of the appropriate topologies and parameters that guarantee the mutual synchronization of the coupled oscillators. This problem has been largely studied in the telecommunications context, with digital hierarchies succeeding at providing precise multiplexing and switching, integrating services, and in the process, giving rise to a new era of communication. From a mathematical viewpoint, this work considers linear coupling factors, with the study of nonlinear effects still open. As the nodes of time distribution networks are phase-locked loops, considering nonlinearities is helpful for the design and operation of such systems. Herein, an overview of possible solutions concerning topologies and parameters is presented, allowing performance hints regarding network architectures and parameters to help designers. The main contribution is to put together and compare each solution while taking nonlinearities into account and to associate the application to be supported with the best clock distribution solution, thus providing simple rules of thumb for system design.

Phase Locking in Millimeter Wave Frequency Synthesizers - Design overview of Charge Pump Phase Locked Loops

Phase Locked Loops are key blocks which are widely adopted in all area of electronics, especially transceivers in wireless communication systems. The application of Phase Locked Loop varies from generation of local oscillator signal for upconversion and down conversion, generation and distribution of clock signals and jitter reduction. The most extensive use of Phase Locked Loop is for frequency synthesis. The requirements of synthesizer architectures depend on various system requirements and specifications which are based on regulatory standards. The design of Phase Locked Loop components involves the consideration of various techniques to resolve the nonidealities at front end high frequency components as well as back end low frequency components. This paper presents the background and importance of a Phase Locked Loop, various approaches over the years, design choices for each block and practical design methodology for Charge Pump Phase Locked Loops. This paper also presents the system level design of Phase Locked Loop and supply noise interactions among sub modules inside a charge pump Phase Locked Loop

Delay-free phase-locked loop ring: Equilibrium and phase perturbation

Clock signal distribution networks have been studied since the 1960s in the search of topologies and parameters that can optimize performance. The problem can be viewed as the mutual synchronization of coupled oscillators, a field being extensively investigated. However, the majority of these investigations consider a linear coupling factor, unlike in the case of time signal distribution systems, wherein nonlinear coupling terms appear. The latter complicates the analysis, mainly because the nodes are phase-locked loops. In the literature pertaining to telecommunications, this problem is studied using linear analysis and is supported by corrections provided by the experimental work. In this paper, a different approach to this problem is presented: here, it is considered that the basic unit of a fully connected time distribution network is a triangular ring of phase-locked loops. The stability of equilibrium states is derived, starting with a delay-free analytical model for the spatial phase and frequency errors. Perturbations of the equilibrium, step, ramp, and accidental phase modulation are included in the model, producing results reflecting the performance of the entire loop.

The DAQ and control system for the CMS Phase-1 pixel detector upgrade

In 2017 a new pixel detector was installed in the CMS detector. This so-called Phase-1 pixel detector features four barrel layers in the central region and three disks per end in the forward regions. The upgraded pixel detector requires an upgraded data acquisition (DAQ) system to accept a new data format and larger event sizes. A new DAQ and control system has been developed based on a combination of custom and commercial microTCA parts. Custom mezzanine cards on standard carrier cards provide a front-end driver for readout, and two types of front-end controller for configuration and the distribution of clock and trigger signals. Before the installation of the detector the DAQ system underwent a series of integration tests, including readout of the pilot pixel detector, which was constructed with prototype Phase-1 electronics and operated in CMS from 2015 to 2016, quality assurance of the CMS Phase-1 detector during its assembly, and testing with the CMS Central DAQ. This paper describes the Phase-1 pixel DAQ and control system, along with the integration tests and results. A description of the operational experience and performance in data taking is included.

Application of VCSELs in next-generation telescope array networks such as the Square Kilometre array

The distribution of precise and accurate optical clock signals across fibre links has a significant impact in various fields. Many applications require the transfer of stable and precise timing signals from a single central location to multiple remote users via a fibre network. One such application is the big data instrument, the Square Kilometre Array (SKA). An increase in demand for more bandwidth by broadband providers has prompted the expansion and development of attractive and intelligent, modern communication networks. Vertical cavity surface-emitting lasers (VCSELs) are an attractive solution and a potential candidate for realizing low cost and high bandwidth data transmission. In this paper a novel and unique, all-optical technique for measuring the one-way transmission time delay of the propagating signal along an optical fibre is presented. This has been successfully achieved by optically injecting a pulse-per-second (PPS) signal into the secondary mode of a 1550 nm VCSEL located at the client end. A round-trip latency time of 113.2 μs was experimentally measured over a 22 km G.652 single mode fibre (SMF). A novel VCSEL capacity upgrade technique is further demonstrate. This was experimentally achieved by simultaneously modulating a single 1310 nm VCSEL with a 10 Gbps 27 − 1 pseudorandom binary sequence (PRBS) and a polarization based PPS clock signal. An error free transmission over 11 km of G.652 SMF was reported, with a measured transmission penalty of 0.52 dB when the VCSEL was simultaneously modulated with the 27 − 1 PRBS and the polarization based PPS signal.

Power efficient synchronous counter design

The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall power of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this brief, we propose a power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The proposed counter design is evaluated and analyzed in terms of power in a standard 45 nm CMOS technology in CADENCE and also evaluated in Synopsys Design Compiler and IC Compiler for ASIC (Application Specific Integrated Circuit) synthesis results. The proposed counter design has lower power requirement and power-area product than existing counter architectures and the power reduction is more significant for wide-bit counters.

Capacity upgrade in short-reach optical fibre networks: simultaneous 4-PAM 20 Gbps data and polarization-modulated PPS clock signal using a single VCSEL carrier

In this work, a four-level pulse amplitude modulation (4-PAM) format with a polarization-modulated pulse per second (PPS) clock signal using a single vertical cavity surface emitting laser (VCSEL) carrier is for the first time experimentally demonstrated. We propose uncomplex alternative technique for increasing capacity and flexibility in short-reach optical communication links through multi-signal modulation onto a single VCSEL carrier. A 20 Gbps 4-PAM data signal is directly modulated onto a single mode 10 GHz bandwidth VCSEL carrier at 1310 nm, therefore, doubling the network bit rate. Carrier spectral efficiency is further maximized by exploiting the inherent orthogonal polarization switching of the VCSEL carrier with changing bias in transmission of a PPS clock signal. We, therefore, simultaneously transmit a 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal using a single VCSEL carrier. It is the first time a signal VCSEL carrier is reported to simultaneously transmit a directly modulated 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal. We further demonstrate on the design of a software-defined digital signal processing (DSP)-assisted receiver as an alternative to costly receiver hardware. Experimental results show that a 3.21 km fibre transmission with simultaneous 20 Gbps 4-PAM data signal and polarization-based PPS clock signal introduced a penalty of 3.76 dB. The contribution of polarization-based PPS clock signal to this penalty was found out to be 0.41 dB. Simultaneous distribution of data and timing clock signals over shared network infrastructure significantly increases the aggregated data rate at different optical network units (ONUs), without costly investment.

Ring-Oscillator Type Multi-Chip Clock Signal Synchronization Technique with In-Phase Clock Bus Lines

This paper suggests a simple method to solve the clock skew problem generated on two or several separate chips when voltage difference, or gradient, occurs between/among the chips. Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today’s GHz operation speed. With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements. With 2% of supplied voltage differences in different chips, within 3% of the period clock skew is guaranteed in this new scheme. A feasible way of implementation of this CBL method in today’s integrated circuits is also described along with CMOS layout.

RF Backplane for MTCA.4-Based LLRF Control System

Low-level RF (LLRF) control systems developed for linear accelerator-based free electron lasers (FELs) require real-time processing of thousands of RF signals with very challenging RF field detection precision. To provide a reliable, maintainable, and scalable system, a new generation of LLRF control based on MTCA.4 architecture was started at DESY for the FLASH and European-XFEL facilities. In contrast to previous RF control systems realized in 19-in modules, we could demonstrate field detection, RF generation, RF distribution, DAQ system, and the high-speed real-time processing entirely embedded in the MTCA.4 crate system. This unique scheme embeds ultra-high-precision analog electronics for detection on the rear transition module (RTM) with powerful digital processing units on the advanced mezzanine card (AMC). To increase system reliability and maintainability and to reduce performance limitations arising through RF cabling, we developed and embedded in the MTCA.4 crate, a unique RF backplane for RTM cards. This backplane is used for distribution of high-performance local oscillator (LO), RF, and low-jitter clock signals together with low-noise analog power supply to analog RTM cards in the system. In this paper, we present the design and architecture of the MTCA.4 crate with the RF backplane and successful test results of the LLRF control system.

High-resolution time synchronization over SpaceWire links

We have demonstrated the benefits of the high-resolution extension to the SpaceWire standard. Initially limited to 280 ns, we are able now to achieve a time-tagging accuracy of 40 ns, which represents a gain by a factor of seven. When in the free-running counter configuration, the highest time resolution could still be achieved even with low SpaceWire data rates. In that case, the time resolution is dramatically increased with our extension with respect to the standard; e.g., the gain is 35 for a data rate of 10 Mbps and a 100-MHz free running counter. As mentioned, the footprint of the extension stays very limited, which allows an easy implementation in any space FPGA. Such an extension combines the benefits of the SpaceWire standard and high-resolution time tagging without the need for another dedicated interface for clock and synchronization signal distribution.

Critical Delays in Clock Distribution Circuits

As the distribution of clock signals between the nodes of a network became a critical operational requisite, the transmission delays have to be studied because they affect the accurate recovering of the time basis. In this work, the critical delay value is calculated considering simplifications compatible with practical situations. The main contribution is to consider the dissipative terms in the node equations, expressing critical delays, depending on the time constant of the dissipation.

FF-EMU: a radiation tolerant ASIC for the distribution of timing, trigger and control signals in the CMS End-Cap Muon detector

A radiation tolerant integrated circuit for the distribution of clock, trigger and control signals in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different latency constraints. Encoder and decoder modules associate signal transitions to FF-LYNX frames. The system and the ASIC architecture and behavior and the results of test and characterization of the ASIC prototypes will be presented.

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

Robust design is a critical concern in ultra-low voltage operation due to large sensitivities to process and environmental variations. In particular, clock networks require careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we propose two complementary methodologies to design robust and low power clock networks at ultra-low voltage regimes, an un-buffered and buffered approach, which can be chosen from depending on the significance of wire resistance. We confirm the efficacy of the proposed strategies through simulations with test circuits over different supply voltages, technologies, and design sizes. We also perform case studies of low voltage clock network design for a microprocessor and signal processing core. For one case study, we employ the un-buffered methodology, reducing +2 σ skew by ~ 5000 × and +2 σ slew by ~ 15% without energy overhead, compared to conventional 1-level buffered H-trees. In the other case, a 3-level buffered tree is implemented, with the proposed clock tree reducing +2 σ skew to ~ 2 % of a clock cycle ( 0.68 × fanout-of-4 delay) and slew variability (σ/μ) to 0.08 at V.

Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter

Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs.

Design constraints for third-order PLL nodes in master-slave clock distribution networks

Clock signal distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the networks, second-order PLLs are adopted due to their simplicity and stability. Nevertheless, in some applications better transient responses are necessary and, consequently, greater order PLLs need to be used, in spite of the possibility of bifurcations and chaotic attractors. Here a master-slave network with third-order PLLs is analyzed and conditions for the stability of the synchronous state are derived, providing design constraints for the node parameters, in order to guarantee stability and reachability of the synchronous state for the whole network. Numerical simulations are carried out in order to confirm the analytical results.

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master–slave architecture with a precise master clock generator sending signals to phase-locked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.

Linear Approach for Synchronous State Stability in Fully Connected PLL Networks

Synchronization is an essential feature for the use of digital systems in telecommunication networks, integrated circuits, and manufacturing automation. Formerly, master‐slave (MS) architectures, with precise master clock generators sending signals to phase‐locked loops (PLLs) working as slave oscillators, were considered the best solution. Nowadays, the development of wireless networks with dynamical connectivity and the increase of the size and the operation frequency of integrated circuits suggest that the distribution of clock signals could be more efficient if distributed solutions with fully connected oscillators are used. Here, fully connected networks with second‐order PLLs as nodes are considered. In previous work, how the synchronous state frequency for this type of network depends on the node parameters and delays was studied and an expression for the long‐term frequency was derived (Piqueira, 2006). Here, by taking the first term of the Taylor series expansion for the dynamical system description, it is shown that for a generic network with N nodes, the synchronous state is locally asymptotically stable.