Abstract

In 2017 a new pixel detector was installed in the CMS detector. This so-called Phase-1 pixel detector features four barrel layers in the central region and three disks per end in the forward regions. The upgraded pixel detector requires an upgraded data acquisition (DAQ) system to accept a new data format and larger event sizes. A new DAQ and control system has been developed based on a combination of custom and commercial microTCA parts. Custom mezzanine cards on standard carrier cards provide a front-end driver for readout, and two types of front-end controller for configuration and the distribution of clock and trigger signals. Before the installation of the detector the DAQ system underwent a series of integration tests, including readout of the pilot pixel detector, which was constructed with prototype Phase-1 electronics and operated in CMS from 2015 to 2016, quality assurance of the CMS Phase-1 detector during its assembly, and testing with the CMS Central DAQ. This paper describes the Phase-1 pixel DAQ and control system, along with the integration tests and results. A description of the operational experience and performance in data taking is included.

Highlights

  • The CMS collaboration has adopted the approach to rely on a highly granular pixel detector as key element for the reconstruction of charged particle tracks and interaction vertices

  • This paper describes the Phase-1 pixel detector data acquisition (DAQ) and control system

  • A rack layout identical to the final setup in the cavern containing all of the production parts, power modules, AC-DC converters, crates, service boards, as well as Front-End Driver (FED) and Front-End Controller (FEC) was operated for several weeks before installation

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Summary

Introduction

The CMS collaboration has adopted the approach to rely on a highly granular pixel detector as key element for the reconstruction of charged particle tracks and interaction vertices. The original CMS pixel detector [3] featured three barrel layers and two forward disks on each end. It was operated during LHC Run 1 (2010–2012) and the first part of Run 2 (2015–2016), and was designed to record efficiently and with high precision the first three space-points of a charged particle track near the interaction region up to an instantaneous luminosity of 1.0 × 1034 cm−2 s−1, with colliding bunch crossings (BX) at a spacing of 25 ns. The original pixel detector would not have sustained a satisfactory performance given the luminosity conditions expected in LHC running after 2017 due to inefficiencies in the front-end readout chip (ROC), and because the maximum throughput rate for the data links of the innermost layer would have been exceeded.

System overview
Readout chips
Token-Bit Manager chip
Optical components
Back-end implementation
DECODE Pixel FED firmware
BUILD Pixel FED firmware
Pixel FED data payload
System tests in the CMS Detector — Phase-1 Pixel Detector Pilot System
System tests in the laboratory
FED tester setup
The DAQ setup for high data rate tests
Pixel online software
Distributed software architecture
Interface to the Detector Control System
Operation performance
Software recovery mechanisms
Periodic ROC resets
Findings
10 Conclusion
Full Text
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