Clock Frequency Research Articles

Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

AbstractA new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16‐, 64‐, 256‐, and 1024‐point FFT architectures. The proposed FFT is designed using Verilog‐HDL and implemented using a Virtex‐7 field‐programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA‐based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state‐of‐the‐art FFT designs. An application‐specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

MC-DPS:Scheduling of mixed-criticality system with dynamic processor speed

MC-DPS:Scheduling of mixed-criticality system with dynamic processor speed

Reduction of light shifts in a cold-atom CPT clock

Light shifts induced during atom–light interactions significantly affect the medium- and long-term frequency stability of atomic clocks. Here, we employ composite laser pulse sequences to mitigate interrogation-induced light shifts in a cold-atom coherent-population-trapping clock. We obtain the anti-symmetry error signal via modulating the local oscillator phase in the free-evolution time of Ramsey interferometry. Utilizing this signal, we employ two feedback loops to simultaneously eliminate light shifts and stabilize the clock frequency using the auto-balanced Ramsey (ABR) spectroscopy scheme. Our experimental results demonstrate that this approach can reduce the clock frequency’s sensitivity to variations in light shifts by implementing four Ramsey sub-sequences. Furthermore, we show that the ABR spectroscopy scheme enhances the long-term frequency stability of the atomic clock when the averaging time τ > 5000 s.

Characteristics of turbulent core–annular flow with water-lubricated high viscosity oil in a horizontal pipe

Direct numerical simulations are performed to investigate the characteristics of a turbulent core–annular flow with water-lubricated high viscosity oil in a horizontal pipe. Six different superficial velocity ratios ( $\,j_w/j_o = 0.057\unicode{x2013}0.41$ ) are examined by changing the water superficial velocity $j_w$ for a fixed oil superficial velocity $j_o$ . The pressure drops in the pipe and the shapes of the phase interface agree well with those from previous experiments. The oil core flow is almost a plug flow, and the gaps between the phase interface and pipe wall are narrow and wide near the upper and lower surfaces of the pipe, respectively, due to the buoyancy. Within a narrow gap, water is confined mostly in a valley region of the wavy phase interface and hardly goes through its crest. On the other hand, water near the phase interface at a wide gap convects downstream almost at the core speed and the flow near the wall is similar to that of single-phase wall-bounded turbulent flow. The annular flow is characterized by three different regimes depending on the clearance Reynolds number ( $Re_c$ ) based on the core velocity and local gap size: laminar Couette flow driven by the core for $Re_c \le 600$ , transitional flow for $600 < Re_c < 2500$ and turbulent flow for $Re_c \ge 2500$ . The minimum pressure drop occurs at $j_w/j_o = 0.11$ in the early transition regime. For all $j_w/j_o$ considered, the negative lift force acting on the core comes from the pressure force which balances the buoyancy.

Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits

This study investigates the timing margin required to handle fluctuations and variations in superconductor single-flux-quantum gate-level-pipelined adders; a smaller timing margin would improve the clock frequencies of gate-level-pipelined circuits. To evaluate timing margins, we demonstrated three 4 bit adders with 50-, 75-, and 100 GHz target clock frequencies using a 1.0 μm process. We estimated that the required timing margin of the adders was 2.1 ps. This indicates that previously reported gate-level-pipelined circuits operating at 30–60 GHz could operate at higher clock frequencies by reducing the timing margins.

Real-time improvement method of turbo-shaft engine component-level model based on dimensional reduction of residual iterative equation

This paper explores a method to improve the real-time computation performance of turbo-shaft engine component-level model by reducing the dimensionality of residual equations set. For turbo-shaft engine, nozzle typically operates in a subcritical working state, assuming that the gas total temperature and pressure parameters of power turbine inlet are the same, and by assuming the gas flow balance between gas generator outlet and nozzle inlet, the iterative solution of the pressure drop of nozzle can be obtained. Then the pressure ratio of power turbine is naturally obtained, thereby achieving the objective of dimensionality reduction of the residual equations set. The component-level model’s steady-state and transient performance were simulated on a desktop computer with a clock frequency of 2.6 GHz. Simulation results show that, with a 2% margin of error, the steady state computation time for the component-level model was reduced by 54.8%, while the transient performance computation time was reduced by 18.6%. This represents a noticeable improvement in real-time performance. Simulation results on the P2020 embedded processor platform with an 800MHz clock frequency indicate a 22.3% reduction in single-step maximum transient performance computation time of the reduced dimensional model, compared to the original model. This demonstrates the effectiveness of dimensionality reduction of the residual equations set in enhancing the model real-time computation performance.

Hybrid Radix-16 Booth encoding and Rounding-based Approximate Karatsuba multiplier for Fast Fourier Transform computation in Biomedical signal processing Application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 , delay is 3.01 ns, power consumption is 0.021mW and power delay product is 119 fJ.

Exploring energy efficiency of LSTM accelerators: A parameterized architecture design for embedded FPGAs

Long Short-Term Memory Networks (LSTMs) are pivotal in on-device time series analysis for embedded systems, particularly for managing sensor data streams. Yet, their deployment on resource-constrained embedded devices presents notable challenges. In response, we introduce a novel parameterized architecture for LSTM accelerators designed explicitly for embedded Field-Programmable Gate Arrays (FPGAs). Our approach involves strategic design choices, such as employing computationally efficient activation functions and optimizing clock frequency with a pipelined Arithmetic Logic Unit (ALU). These decisions drive our architecture towards enhanced energy efficiency while maintaining adaptability across diverse application scenarios. A key feature of our architecture is its configurable parameters, which allow for tailored optimization through the optional use of Digital Signal Processor Slices for ALUs and the selective implementation of activation functions. Our empirical evaluations conducted on the Spartan-7 XC7S15 FPGA demonstrate the robustness of our methodology, achieving a 2.33× improvement in energy efficiency over previous solutions. Furthermore, our study examines the correlation between memory resource types and energy efficiency across various LSTM model sizes. Impressively, even with a 9× increase in the hidden size of the LSTM cell, our accelerator maintains an energy efficiency of 10.03 GOP/s/W, with only a minor decrease of 14.65%. However, it is critical to note that our current design is not yet optimized for larger FPGA models such as the Spartan-7 XC7S25 and XC7S50. For these models, timing constraints, rather than resource limitations, pose challenges to scaling, highlighting a potential area for future optimization.

Identification of novel pharmacological activators of circadian clock with anti-adipogenic properties

The circadian clock drives rhythmic oscillations of metabolic processes to orchestrate metabolic homeostasis, and disruption of this mechanism predisposes to obesity and insulin resistance. Preserving or augmenting clock function could be a potential therapeutic target for metabolic diseases, particularly with the wide-spread of circadian misalignment in a modern lifestyle. To date, targeting the clock for metabolic disease prevention or treatment remains to be explored. Adipocyte possesses cell-autonomous clocks that exert transcriptional control of the Wnt pathway to inhibit adipocyte development. Using a high through-put screening pipeline, we recently identified Chlorhexidine as a novel clock-activating molecule that targets the key driver of the circadian clock transcriptional feedback loop, the CLOCK protein. Based on clock function in suppressing adipogenesis, we hypothesize that Chlorhexidine and related compounds may possess adipogenic-inhibitory properties suitable for anti-obesity drug development. In distinct adipogenic progenitor models, we demonstrate the activity of Chlorhexidine in inhibiting adipogenic lineage commitment and terminal differentiation. Furthermore, we report the structural optimization of Chlorhexidine chemical scaffold that led to the discovery of new analogs with improved anti-adipogenic effcacy. Consistent with its activity for clock activation, in adipogenic progenitors containing a Period2::dLuc luciferase reporter, Chlorhexidine induced significant shortening of clock period length with induction of core clock components. Chlorhexidine treatment of adipogenic mesenchymal precursors robustly suppressed their adipogenic maturation, with a comparable effect observed on inhibiting terminal differentiation of primary preadipocytes in a clock-dependent manner. Mechanistically, Chlorhexidine stimulates clock-controlled Wnt signaling that mediates its anti-adipogenic effect. Through medicinal chemistry modification of its chemical scaffold, we generated a panel of Chlorhexidine analogs with validation for their clock-modulatory activities. Structure activity relationship analysis of these analogs led to the identification of CM002 as a new clock activator with improved clock-dependent anti-adipogenic activity. Collectively, our findings uncovered a new class of clock-modulatory compounds that inhibit adipocyte development for potential anti-obesity drug discovery and provide clock-targeting chemical probes for dissecting clock function in metabolic physiology. This project was supported by grants from National Institute of Aging R56AG080294 and Arthur Riggs-Diabetes & Metabolism Research Institute T2D and T1D Innovative Awards to KM. This is the full abstract presented at the American Physiology Summit 2024 meeting and is only available in HTML format. There are no additional versions or additional content available for this abstract. Physiology was not involved in the peer review process.

Phylogeny and biogeography of harmochirine jumping spiders (Araneae: Salticidae)

We use ultraconserved elements (UCE) genomic data to study the phylogeny, age, and biogeographical history of harmochirine jumping spiders, a group that includes the species-rich genus Habronattus, whose remarkable courtship has made it the focus of studies of behaviour, sexual selection, and diversification. We recovered 1947 UCE loci from 43 harmochirine taxa and 4 outgroups, yielding a core dataset of 193 UCEs with at least 50 % occupancy. Concatenated likelihood and ASTRAL analyses confirmed the separation of harmochirines into two major clades, here designated the infratribes Harmochirita and Pellenita. Most are African or Eurasian with the notable exception of a clade of pellenites containing Habronattus and Pellenattus of the Americas and Havaika and Hivanua of the Pacific Islands. Biogeographical analysis using the DEC model favours a dispersal of the clade’s ancestor from Eurasia to the Americas, from which Havaika’s ancestor dispersed to Hawaii and Hivanua’s ancestor to the Marquesas Islands. Divergence time analysis on 32 loci with 85 % occupancy, calibrated by fossils and island age, dates the dispersal to the Americas at approximately 4 to 6 million years ago. The explosive radiation of Habronattus perhaps began only about 4 mya. The phylogeny clarifies both the evolution of sexual traits (e.g., the terminal apophyses was enlarged in Pellenes and not subsequently lost) and the taxonomy. Habronattus is confirmed as monophyletic. Pellenattus is raised to the status of genus, and 13 species moved into it as new combinations. Bianor stepposus Logunov, 1991 is transferred to Sibianor, and Pellenes bulawayoensis Wesołowska, 1999 is transferred to Neaetha. A molecular clock rate estimate for spider UCEs is presented and its utility to inform prior distributions is discussed.

Secured V2X communication using optimized prime field ECC architecture

The objective of this research is to ensure a high level of security in various forms of vehicular communication (V2V, V2I, and V2N) and to support vehicles in safely receiving all keys and messages from Roadside Unit (RSU), other vehicles, or the network with the support of simple cryptographic techniques. Elliptic Curve Cryptography (ECC) is one of the many cryptographic techniques that offer a desirable response to this requirement. The Koblitz curve secp256k1 is supported by the designed ECC processor for 256-bit point multiplication and point addition. A powerful illustration of the "Divide and Conquer" strategy's ability to accelerate multiplication asymptotically is given by the Karatsuba algorithm. The ECC processor's multiplication operation is accelerated further by the incorporation of pipelining. With a maximum clock frequency of 238.40MHz, the proposed Karatsuba-based ECC processor executes 256-bit single point multiplication in 0.937ms, providing 273.21kbps throughput, and taking up 8.42k slices in a Virtex-7 FPGA. Scalar multiplication is extended by incorporating a pipeline by increasing the highest clock frequency by up to 7.97%, which decreases time consumption by 9.90% and boosts throughput by 10.99%. In terms of area, operating frequency, area-delay product, and throughput, the suggested pipelined Karatsuba multiplier based ECC processor performs better than the existing designs.

Direct Digital RF Transceiver Technology for Millimeter‐Wave DBF Systems

AbstractDigital RF technology has been developed and has been applied to below 6 GHz wireless applications. By replacing the IC die consumptive RF/analog circuit blocks by digital signal processor and circuit, digital rich/small transceivers can be realized. Since the foundation of this technology is based on the Nyquist theory, the operational frequency of the circuit has been limited by the Nyquist frequency (=1/2 of sampling clock frequency). As a result, the maximum operational RF frequency of existing digital RF technology was below 6 GHz. In this paper, a new direct digital RF technology that utilizes the higher‐order Nyquist zones is introduced. This technology enables handling RF signal in beyond Nyquist frequency range which means over 6 GHz range. The results of fabricated 26/28 GHz‐band transmitter/receiver are reviewed. Since the transceiver architecture with the proposed technologies does not require an RF local oscillator and up/down converters, it is suitable for microwave/millimeter‐wave multi‐antenna systems such as next generation satellite on‐board digital beam forming and Beyond 5G fully digital Massive multiple‐input multiple‐output systems.

Derivative Pricing using Quantum Signal Processing

Pricing financial derivatives on quantum computers typically includes quantum arithmetic components which contribute heavily to the quantum resources required by the corresponding circuits. In this manuscript, we introduce a method based on Quantum Signal Processing (QSP) to encode financial derivative payoffs directly into quantum amplitudes, alleviating the quantum circuits from the burden of costly quantum arithmetic. Compared to current state-of-the-art approaches in the literature, we find that for derivative contracts of practical interest, the application of QSP significantly reduces the required resources across all metrics considered, most notably the total number of T-gates by ∼16x and the number of logical qubits by ∼4x. Additionally, we estimate that the logical clock rate needed for quantum advantage is also reduced by a factor of ∼5x. Overall, we find that quantum advantage will require 4.7k logical qubits, and quantum devices that can execute 109 T-gates at a rate of 45MHz. While in this work we focus specifically on the payoff component of the derivative pricing process where the method we present is most readily applicable, similar techniques can be employed to further reduce the resources in other applications, such as state preparation.

Development of a facial recognition model using optimized convolution neural network with Tiny-ML and fingerprint authentication for safe lock entry

Safe boxes have been used for centuries to protect valuable items, and their design and construction have evolved over time to improve security. In this study, we carried out the design and implementation of a facial recognition technology using optimized convolutional neural networks (CNNs) with TinyML and fingerprint. The facial recognition system is designed using pre-trained CNN architectures then optimized with TinyML to make it fit into resource constrained edge device, the fingerprint recognition is designed using ridge matching biometric algorithm which fits in perfectly into the microcontroller-based system. The safe box was fabricated using sheet metal and insulated using heat resistive material (fiber glass), components like OV2640 camera module, ESP32-S3, R305 Fingerprint sensor, 4.3 inches touch screen TFT display and a charging module to manage and charge the systems battery were used. The system was implemented to be a level two security and two-way verification system using secured Wi-Fi to access the system before the facial and fingerprint recognition functionality is activated, the sequence of operation can either be facial recognition before fingerprint recognition or fingerprint recognition before facial recognition. Evaluating the system’s facial recognition performance with confusion matrix, of all the optimized CNN architectures like VGGNet, SENet, RestNet, MobileNet-V2, EfficientNet-B0, SENet Architecture performed best outputting an accuracy of 98%, precision of 92%, also SENet unoptimized model performed same, MobileNet-V2 performed optimally in the inference speed test with a speed of 15ms/images with the fingerprint also evaluated using confusion matrix and perform with 98% accuracy. It was noticed that the inference speed of the unoptimized model is faster than that of the TinyML optimized model which is justifiable based on the processing clock speed, memory usage, GPU and architecture of the microcontroller/microprocessor. From the result obtained TinyML proves to be suitable mean for edge AI (artificial intelligence) and is recommended for future research and development.

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.

FPGA Implementation of a Pipelined Kalman Filter for Object Tracking in Two Dimensions

In a location tracking system for a moving object, not only accuracy but also real-time processing are important factors. The Kalman filter, as a recursive function, stands out as one of the prominent algorithms for object tracking. It continuously compares measured data with predicted values based on the system characteristics in real time, and then corrects the error of the predicted values while considering the noise of both system and measured data. This paper focuses on designing a hardware-based Kalman filter for object tracking in two dimensions. Following an analysis of the Kalman filter algorithm, the blocks capable of parallel processing are identified and configured to be processed in parallel, effectively reducing data processing time. The clock speed is enhanced by using the pipeline technique. In addition, the time-sharing technique is applied to increase the utilization of hardware resources and reduce the area. Data was processed at 32-bit floating points to uphold accuracy comparable to software-implemented Kalman filters. The proposed Kalman filter architecture is designed using verilog HDL and then simulated in Synopsys VCS/Verdi. And the accuracy is verified by comparing results with a software-based Kalman filter designed using MATLAB. It was implemented using Zynq ZYNQ-7 ZC702 Programmable logic via Xilnix Vivado, and can operate at 33MHz. It takes a total of 44 clocks, or 1.32 us, to process one data. Therefore, it was confirmed that the designed Kalman filter hardware is suitable for real-time processing.

FPGA-based fast bin-ratio spiking ensemble network for radioisotope identification

In this work, we demonstrate the training, conversion, and implementation flow of an FPGA-based bin-ratio ensemble spiking neural network applied for radioisotope identification. The combination of techniques including learned step quantisation (LSQ) and pruning facilitated the implementation by compressing the network’s parameters down to 30% yet retaining the accuracy of 97.04% with an accuracy loss of less than 1%. Meanwhile, the proposed ensemble network of 20 3-layer spiking neural networks (SNNs), which incorporates 1160 spiking neurons, only needs 334 μs for a single inference with the given clock frequency of 100 MHz. Under such optimisation, this FPGA implementation in an Artix-7 board consumes 157 μJ per inference by estimation.

Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done. Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics