Improving the computational efficiency of lock-in algorithms through coherent averaging

Abstract

The lock-in amplifier and coherent averaging, established techniques for processing periodic signals, are combined in a novel system. In this approach, the signal is first averaged coherently for a number of periods and then passed through a lock-in with moving average filter of a whole number of periods as low-pass filter. Results match those obtained with traditional lock-in with moving average filter, but maximizing the number of cycles used for the coherent average significantly reduces the multiplications involved in the calculation. Any lock-in system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.