Clock Phase Research Articles

Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.

Delaying circadian sleep phase under ultradian light cycle causes time-of-day-dependent alteration of cognition and mood

Light exerts powerful and pervasive effects on physiology and behaviour. These effects can be indirect, through clock synchronization and phase adjustment of circadian rhythms, or direct, independent of the circadian process. Exposure to light at inappropriate times, as commonly experienced in today’s society, leads to increased prevalence of circadian, sleep and mood disorders as well as cognitive impairments. In mice, exposure to an ultradian 3.5 h light/3.5 h dark cycle (T7) for several days has been shown to impair behaviour through direct, non-circadian, photic effects, a claim we challenge here. We first confirmed that T7 cycle induces a lengthening of the circadian period resulting in a day by day phase-delay of both activity and sleep rhythms. Spatial novelty preference test performed at different circadian time points in mice housed under T7 cycle demonstrated that cognitive deficit was restrained to the subjective night. Mice under the same condition also showed a modification of stress-induced despair-like behaviour in the forced swim test. Therefore, our data demonstrate that ultradian light cycles cause time-of-day-dependent alteration of cognition and mood through clock period lengthening delaying circadian sleep phase, and not through a direct photic influence. These results are of critical importance for the clinical applications of light therapy in the medical field and for today’s society to establish lighting recommendations for shift work, schools, hospitals and homes.

Mechanical loading and hyperosmolarity as a daily resetting cue for skeletal circadian clocks

Daily rhythms in mammalian behaviour and physiology are generated by a multi-oscillator circadian system entrained through environmental cues (e.g. light and feeding). The presence of tissue niche-dependent physiological time cues has been proposed, allowing tissues the ability of circadian phase adjustment based on local signals. However, to date, such stimuli have remained elusive. Here we show that daily patterns of mechanical loading and associated osmotic challenge within physiological ranges reset circadian clock phase and amplitude in cartilage and intervertebral disc tissues in vivo and in tissue explant cultures. Hyperosmolarity (but not hypo-osmolarity) resets clocks in young and ageing skeletal tissues and induce genome-wide expression of rhythmic genes in cells. Mechanistically, RNAseq and biochemical analysis revealed the PLD2-mTORC2-AKT-GSK3β axis as a convergent pathway for both in vivo loading and hyperosmolarity-induced clock changes. These results reveal diurnal patterns of mechanical loading and consequent daily oscillations in osmolarity as a bona fide tissue niche-specific time cue to maintain skeletal circadian rhythms in sync.

The Implementation of Precise Point Positioning (PPP): A Comprehensive Review.

High-precision positioning from Global Navigation Satellite Systems (GNSS) has garnered increased interest due to growing demand in various applications, like autonomous car navigation and precision agriculture. Precise Point Positioning (PPP) offers a distinct advantage over differential techniques by enabling precise position determination of a GNSS rover receiver through the use of external corrections sourced from either the Internet or dedicated correction satellites. However, PPP's implementation has been challenging due to the need to mitigate numerous GNSS error sources, many of which are eliminated in differential techniques such as Real-Time Kinematics (RTK) or overlooked in Standard Point Positioning (SPP). This paper extensively reviews PPP's error sources, such as ionospheric delays, tropospheric delays, satellite orbit and clock errors, phase and code biases, and site displacement effects. Additionally, this article examines various PPP models and correction sources that can be employed to address these errors. A detailed discussion is provided on implementing the standard dual-frequency (DF)-PPP to achieve centimeter- or millimeter-level positioning accuracy. This paper includes experimental examples of PPP implementation results using static data from the International GNSS Service (IGS) station network and a kinematic road test based on the actual trajectory to showcase DF-PPP development for practical applications. By providing a fusion of theoretical insights with practical demonstrations, this comprehensive review offers readers a pragmatic perspective on the evolving field of Precise Point Positioning.

A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability

A fractional-N frequency synthesizer (FS) with phase synchronization and programmable phase control capacity is proposed. The issue of phase inconsistency among multiple FSs caused by the shift of delta-sigma modulator (DSM) output sequence is solved by means of the dual DSM switching technique. Following the FS core, a resettable divider (R-DIV) is presented, which can not only expand the final output frequency range, but also eliminate the phase uncertainty incurred by uncontrollable initial states inherent in the ordinary dividers. By adding initial values to the first order accumulator in the third-order DSM, the output clock phase of the FS can be controlled accordingly. The simulation results show that from a supply voltage of 1.2 V, the frequency range of the FS is 0.4∼12 GHz, and the phase synchronization time is < 10 μs. The minimum phase shift step size of the programmable phase control is 5.625°, the RMS phase error is < 0.9°, and the power consumption is 113.7 mW.

Design of a Novel Decimal to Multicode Converter in QCA Technology

Researchers are always looking for the improvement of existing methods. Today, CMOS technology is widely used, which has some advantages and disadvantages. One of the alternative methods for CMOS technology is QCA technology which compared to CMOS, has the advantages of low energy consumption and small occupied area. In this paper, by using the concepts and methods of QCA technology, a digital code converter is presented. In this converter, a new gate is used, which can produce outputs such as 4-input AND, 4-input OR, 4-input NAND, and 4-input NOR. The proposed converter has 10 inputs and 12 outputs. The 10 inputs are decimal numbers from 0 to 9, producing the output equivalent to excess-3, BCD, and gray codes. One of the advantages of this circuit is providing three different codes per input in just one circuit. In addition, due to the use of the new 4-input gate, the occupied area and the number of used cells were minimized. Simulations were performed by using QCADesigner-E version 2.2, and outcomes illustrated that the occupied area is equal to 0.29 μm2 and 380 QCA cells with 7 clock phases are used. The energy dissipation of the presented circuit is 171 meV. Also, given the favorable performance exhibited by the 4-input gate across various measurement parameters, it possesses the capability to be efficiently employed within larger and intricately designed circuits.

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

Leptin receptor neurons in the dorsomedial hypothalamus input to the circadian feeding network.

Salient cues, such as the rising sun or availability of food, entrain biological clocks for behavioral adaptation. The mechanisms underlying entrainment to food availability remain elusive. Using single-nucleus RNA sequencing during scheduled feeding, we identified a dorsomedial hypothalamus leptin receptor-expressing (DMHLepR) neuron population that up-regulates circadian entrainment genes and exhibits calcium activity before an anticipated meal. Exogenous leptin, silencing, or chemogenetic stimulation of DMHLepR neurons disrupts the development of molecular and behavioral food entrainment. Repetitive DMHLepR neuron activation leads to the partitioning of a secondary bout of circadian locomotor activity that is in phase with the stimulation and dependent on an intact suprachiasmatic nucleus (SCN). Last, we found a DMHLepR neuron subpopulation that projects to the SCN with the capacity to influence the phase of the circadian clock. This direct DMHLepR-SCN connection is well situated to integrate the metabolic and circadian systems, facilitating mealtime anticipation.

Flip Flops Design in Quantum Dot Cellular Automata Technology: Towards Digitization

Quantum-Dot Cellular Automata (QCA) is a transistor-less technology. In QCA, Columbic repulsion between electrons in the quantum dots makes data transfer possible. This paper presents the design of flip flops using a proposed Rotated-Normal Cells with Displacement (RND) inverter and a cell interaction method. The SR latch, SR Flip Flop (FF), D FF, and T FF are developed using QCA. The proposed D FF gives total and average energy dissipation of 1.31e-002eV and 1.19e-003eV respectively. It also gives a delay of 1 clock phase. The Proposed T FF provides total and average energy dissipation of 2.40e-002eV and 2.18e-003eV respectively, depicting efficient D FF and T FF in energy dissipation. The proposed SR Flip flop design gives an efficient area. The FFs with the proposed RND inverter and cell interaction method can be the best choice for future Nano communication to construct Nano circuits with less energy dissipation and high speed.

Low-latency wavelength-switched clock-synchronized intra-data center interconnects enabled by hollow core fiber.

Fast (nanoseconds) optical wavelength switching is emerging as a viable solution to scaling the size and capacity of intra-data center interconnection. A key enabling technology for such systems is low-jitter optical clock synchronization, which enables sub-nanosecond clock and data recovery for optically switched frames using low-cost methods such as clock phase caching. We propose and demonstrate real-time low-latency wavelength-switched clock-synchronized intra-data center interconnection at 51.2 GBd using a fast tunable laser (with ns scale switching time) and ultra-stable-latency hollow core fiber (HCF) for optically-switched data center networks. For wavelength-switched systems, we achieve a physical layer latency below 46 ns, consisting of 28 ns transceiver latency and a 18 ns inter-packet gap. Finally, we show that by exploiting the low chromatic dispersion and thermally-stable latency features of HCF, active clock phase tracking can be entirely eliminated.

An Extended Range Divider Technique for Multi-Band PLL

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.

A negative voltage generator with 4-stage configurable parallel switching for smart window film applications

ABSTRACT A negative voltage generator was developed that can be used in the drivers of smart window films (SWF), which have typical operating voltages of 8 to 10 V. It consists of four Negative Charge Pump (NCP) stages and a 4-phase non-overlapping Clock Generator (CG), where the 4 NCP stages are configurable by external digital signals. This generates a wide output voltage range necessary to control different SWF modes, such as opaque, transparent, and tinted modes. TSMC 0.18-m HV BCD (High-Voltage Bipolar-CMOS-DMOS) process was used to fabricate the proposed negative voltage generator on silicon. Measurement results demonstrate that at switching frequency (fsw) = 20 MHz, supplied voltage (VDD) = 4.5 V and Vin = GND, it generates a wide output voltage range of −3.9 to −14.0 V, achieving the widest voltage range among the prior works, which covers the required negative voltage range for SWF usage. The peak efficiency is measured on silicon to be 58.08% .

Effects of the Light/Dark Phase and Constant Light on Spatial Working Memory and Spine Plasticity in the Mouse Hippocampus.

Circadian rhythms in behavior and physiology such as rest/activity and hormones are driven by an internal clock and persist in the absence of rhythmic environmental cues. However, the period and phase of the internal clock are entrained by the environmental light/dark cycle. Consequently, aberrant lighting conditions, which are increasing in modern society, have a strong impact on rhythmic body and brain functions. Mice were exposed to three different lighting conditions, 12 h light/12 h dark cycle (LD), constant darkness (DD), and constant light (LL), to study the effects of the light/dark cycle and aberrant lighting on the hippocampus, a critical structure for temporal and spatial memory formation and navigation. Locomotor activity and plasma corticosterone levels were analyzed as readouts for circadian rhythms. Spatial working memory via Y-maze, spine morphology of Golgi-Cox-stained hippocampi, and plasticity of excitatory synapses, measured by number and size of synaptopodin and GluR1-immunreactive clusters, were analyzed. Our results indicate that the light/dark cycle drives diurnal differences in synaptic plasticity in hippocampus. Moreover, spatial working memory, spine density, and size and number of synaptopodin and GluR1 clusters were reduced in LL, while corticosterone levels were increased. This indicates that acute constant light affects hippocampal function and synaptic plasticity.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

Sequential Generation of Multi-GNSS Multi-Frequency PPP-RTK Products and Their Performance Using the EUREF Permanent GNSS Network

In the classic Precise Point Positioning (PPP) approach, observations of Global Navigation Satellite Systems (GNSS) are processed at the network level to generate satellite clocks and positions. This information can be used to enable accurate point positioning for a single GNSS receiver. In the PPP Real-Time Kinematic (PPP-RTK) approach, satellite phase biases are considered as well, enabling ambiguity resolution at the network and user levels. In this research, 30 s multi-frequency raw GPS, Galileo, and BDS-2/3 observations are processed at the network and user levels in a sequential Kalman filter. PPP-RTK enabling products are generated for up to five frequencies, and ambiguity resolution is performed at the network and user levels using a flexible ambiguity reparameterization approach, comparable to wide- and narrow-laning, which has shown to yield a significantly improved single epoch coordinate solution when multi-frequency observations are available. Different assumptions regarding the time stability of receiver and satellite phase biases have been made and compared. The availability of a precise user coordinate solution when multi-frequency and dual-frequency observations are processed is assessed and compared. A precise ambiguity-fixed solution is available in three epochs or fewer in 77% of all cases with an average of 24 visible satellites for static and kinematic receivers when multi-frequency observations are processed. When only dual-frequency observations are considered, a fixed solution is available in seven epochs or fewer in 71% of all cases. The fastest fixed solution was found in two epochs with multi-frequency observations and in six epochs with dual-frequency observations. Estimating a reference phase clock did not lead to an improvement in the coordinate solution. The findings indicate that a fixed solution can potentially be found faster than often suggested, with potential for further improvement when more satellites or regional atmospheric corrections are considered.

Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

Mice with humanized livers reveal the role of hepatocyte clocks in rhythmic behavior.

The synchronization of circadian clock depends on a central pacemaker located in the suprachiasmatic nuclei. However, the potential feedback of peripheral signals on the central clock remains poorly characterized. To explore whether peripheral organ circadian clocks may affect the central pacemaker, we used a chimeric model in which mouse hepatocytes were replaced by human hepatocytes. Liver humanization led to reprogrammed diurnal gene expression and advanced the phase of the liver circadian clock that extended to muscle and the entire rhythmic physiology. Similar to clock-deficient mice, liver-humanized mice shifted their rhythmic physiology more rapidly to the light phase under day feeding. Our results indicate that hepatocyte clocks can affect the central pacemaker and offer potential perspectives to apprehend pathologies associated with altered circadian physiology.

Performance optimization of the nano-scale carry-skip adder based on quantum dots and its application in the upcoming Internet of Things

Internet of Things (IoT) is a network of linked computers, electronic and mechanical equipment, objects, living things, and people that can exchange data without human-to-human or human-to-computer interaction. Real objects with sensors, computing power, software, and other technologies are called IoT when they connect to and exchange data with other systems and devices over the Internet or other communication networks. On the other hand, Quantum-dot Cellular Automata (QCA) is a highly appealing alternative to transistor-based technologies for future circuit design, thanks to its excellent performance and low power consumption characteristics. Therefore, researchers are trying to implement IoT-related circuits in this technology and take advantage of it. In IoT nodes, the circuits were previously designed based on transistors and used extensively are adder circuits and their various forms, such as carry-look-ahead adder, ripple carry adder, and Carry-Skip Adder (CSA). The proposed CSA is part of the bypass adder family, and its major goal in IoT devices is to reduce latency and power consumption. Designing CSA is a fascinating area of research in the QCA and IoT domains. In this research, we will offer nano-scale CSA designs based on logic gate structures. This CSA aids in improving system performance in terms of average power dissipation, area, and delay. This design has performed admirably in terms of physical qualities, particularly power usage. As a result, an ultra-low-power CSA is proposed, which employs a reduced number of cells and a smaller area while achieving the desired highly polarized output. All the circuits provided in the simulator software have been tested, and their correctness has been confirmed. 36 quantum cells were employed, and the adder's area with propagating signal is around 0.04 µm2. The latency is about 2 clock phases. Additionally, the CSA for IoT devices is roughly 0.4 µm2, which results in a delay of 17 clock phases and the need for 374 quantum cells. The suggested CSA reduces cell consumption by 64 %, improves latency by 15 %, and increases area by 85 %. Compared to a carry-look-ahead adder, the CSA is the only way to reduce the latency of a ripple carry adder with low effort.

D-Glucosamine induces circadian phase delay by promoting BMAL1 degradation through AMPK/mTOR pathway

Circadian rhythms are closely linked to the metabolic network through circadian feedback regulation. The hexosamine biosynthetic pathway (HBP) is a branch of glucose metabolism that affects circadian rhythms through the O-linked N-acetylglucosamine modification (O-GlcNAcylation) of clock proteins. Here, we found out that, among the downstream metabolites regulated by d-glucosamine (GlcN) in HBP salvage pathway, only GlcN is able to induce circadian phase delay both in vitro and in vivo. Mechanistic studies indicated that the phase-shift induced by GlcN is independent of O-GlcNAcylation. Instead, GlcN selectively up-regulates p-AMPK activity, leading to the inhibition of mTOR signaling pathway, and thus down-regulation of p-BMAL1 both in human cell line and mouse tissues. Moreover, GlcN promoted BMAL1 degradation via proteasome pathway. These findings reveal a novel molecular mechanism of GlcN in regulating clock phase and suggest the therapeutic potential of GlcN as new use for an old drug in the future treatment of shift work and circadian misalignment.

Design and Implementation of Precision Phase Measurement Module Base on Digital Dual Mixer Time Difference

Precise phase difference measurement is critical for distributed time synchronization systems. Aiming at the problem of how to realize the sub-nanosecond phase difference measurement of the time signal, the digital dual mixer time difference (DDMTD) measurement technology is used to measure the fine transmission delay and the two digital clock phase difference. Given the problem that it is difficult to generate a common clock source with fine frequency changes inside the FPGA chip, the Si5338 chip is used to generate 4 differential clocks, and the communication with the FPGA is completed through the I2C protocol, and the differential signal is converted into a single-ended clock source inside the FPGA as two The common standard frequency of clock signals with the same frequency and different phases, realize the amplification of the phase difference measurement range, making the measurement accuracy reach sub-nanosecond level.