Clock Domains Research Articles

Fixed-Latency Gigabit Serial Links in a Xilinx FPGA for the Upgrade of the Muon Spectrometer at the ATLAS Experiment

We present an implementation of fixed-latency gigabit serial links in a low-cost Xilinx field-programmable gate array. The implementation is targeted for a data packet router in the upgrade of the ATLAS muon spectrometer. The router serves as a packet switch. It handles up to 12 serial inputs at 4.8 Gbps from on-detector electronics and four 4.8-Gbps outputs to the trigger processing circuits. The input serial streams are deserialized and aligned to a common clock domain for NULL suppression and data packet forwarding. Gigabit transceivers are used in the processing, and a scheme is developed to maintain low and fixed-latency packet multiplexing through the router. We analyze the latency of the scheme and demonstrate its performance in a setup similar to that of the final detector arrangement.

Refined metastability characterization using a time-to-digital converter

In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter to the output of the flip flop under test, rather than using a phase shifted clock, as conventionally done. We present the details of an FPGA implementation of our approach and show its feasibility through an experimental evaluation, whose results favorably match those obtained by the conventional method. The benefits of the novel scheme are the ability to perform a calibration for the delay steps, a speed-up of the measurement process, and the availability of a more comprehensive and ordered measurement data set. Especially the latter can be of crucial importance when (even multiple) glitches or oscillation are suspected to result from metastability, or when the temporal distribution of upsets matters (bursts of upsets, e.g.).

A Dual-Clock Multiple-Queue Shared Buffer

Multiple parallel queues are versatile hardware data structures that are extensively used in modern digital systems. To achieve maximum scalability, the multiple queues are built on top of a dynamically-allocated shared buffer that allocates the buffer space to the various active queues, based on a linked-list organization. This work focuses on dynamically-allocated multiple-queue shared buffers that allow their read and write ports to operate in different clock domains. The proposed dual-clock shared buffer follows a tightly-coupled organization that merges the tasks of signal synchronization across asynchronous clock domains and queueing (buffering), in a common hardware module. When compared to other state-of-the-art dual-clock multiple-queue designs, the new architecture is demonstrated to yield a substantially lower-cost implementation. Specifically, hardware area savings of up to 55 percent are achieved, while still supporting full-throughput operation.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

KiloCore: A 32-nm 1000-Processor Computational Array

A processor array containing 1000 independent processors and 12 memory modules was fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable processors occupy 0.055 mm2 each, contain no algorithm-specific hardware, and operate up to an average maximum clock frequency of 1.78 GHz at 1.1 V. At 0.9 V, processors operating at an average of 1.24 GHz dissipate 17 mW while issuing one instruction per cycle. At 0.56 V, processors operating at an average of 115 MHz dissipate 0.61 mW while issuing one instruction per cycle, resulting in an energy consumption of 5.3 pJ/instruction. On-die communication is performed by complementary circuit and packet-based networks that yield a total array bisection bandwidth of 4.2 Tb/s. Independent memory modules handle data and instructions and operate up to an average maximum clock frequency of 1.77 GHz at 1.1 V. All processors, their packet routers, and the memory modules contain unconstrained clock oscillators within independent clock domains that adapt to large supply voltage noise. Compared with a variety of Intel i7s and Nvidia GPUs, the KiloCore at 1.1 V has geometric mean improvements of 4.3 $\times$ higher throughput per area and 9.4 $\times$ higher energy efficiency for AES encryption, 4095-b low-density parity-check decoding, 4096-point complex fast Fourier transform, and 100-B record sorting applications.

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.

Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication

Double-edged pulsewidth modulation (DPWM) is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with $10^{-12}$ bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead.

FSM Based DFS Link for Network on Chip

As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor

The SPARC M7 processor offers up to 3 $\times$ the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support for VIS extensions, virtual address masking, and user-level synchronization instructions to provide substantial single thread performance over the predecessor design. A total of 256 threads per chip provide the throughput performance required by even the most demanding enterprise applications. Both throughput and single thread performance benefit from a large fully shared 64 MB on-chip L3 cache with very low latency. The 0.5 TB/s on-chip communications bandwidth requirements are served via a semi-custom on-chip network (OCN) in place of the traditional crossbar. Hardware database analytics accelerator units (DAX) achieve up to 10 $\times$ the performance for in-memory database queries, include decompression and messaging operations, and support pointer version checking for securing application data through application data integrity (ADI), as well as fine grained memory migration. The SerDes IO operate up to 18 Gbps, offering 1 TB/s total bandwidth for memory and multi-socket interfaces. New on-chip power management features include fast and accurate dynamic power meters, thermal sensors, and a fine-grain thermal, current, and chip power control engine to enable maximum performance/Watt. Special circuits like the voltage shift module (VSM) were developed to cope with the clock and voltage domain crossing issues, while the asymmetric frequency lock loop (AFLL) main clock generation circuit also provides Ldi/dt droop compensation leading to substantial power savings.

Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control

This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systems-on-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock.

K Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching

Nearest-neighbor-search classifiers are attractive but they have high intrinsic computational demands which limit their practical application. In this paper, we propose a coprocessor for k (k with k≥1) nearest neighbor (kNN) classification in which squared Euclidean distances (SEDs) are mapped into the clock domain for realizing high search speed and energy efficiency. The minimal SED searching is carried out by weighted frequency dividers that drastically reduce the normally exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This also results in low power dissipation and high area-efficiency in comparison to the traditional method using large numbers of adders and comparators. The kNN classifier determines the class of an unknown input sample with a majority decision among the k nearest reference samples. The required majority-decision circuit is integrated with the clock-mapping-based minimal-SED searching architecture and proceeds with the classification immediately after identification of each of the k nearest references. A test chip in 180 nm CMOS technology, which can process 8 dimensions of 32 reference vectors in parallel, achieves low power dissipation of 40.32 mW (at 51.21 MHz clock frequency and 1.8 V supply voltage). Significantly, the distance search circuit consumes only 5.99 mW. Feature vectors with different dimensionality up to 2048 dimensions can be handled by the designed coprocessor due to a dimension extension circuit, enabling large flexibility for usage in different application.

Variability in Multistage Synchronizers

System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the different clock domains. To achieve high reliability margins in high-frequency designs implemented in modern process technologies, multistage synchronizers are often used. In this paper, we develop analytical formulas to calculate the probability of failure and the number of stages to use in such synchronizers. We compare our model with those reported in previous publications and show that most existing models underestimate mean time between failures (MTBF). Our model calculates an MTBF lower bound with significantly smaller margins. The concept of an effective resolution time constant for multistage synchronizers is introduced and the important effects of clock duty cycle and process variability are addressed. These process variability effects can be minimized by use of simple design rules for the synchronizer. For safety-critical applications, calculation of the probability of a failure-free lifetime for all products in a production run is developed and a simple lower bound is derived.

Design of a Digitalized Microgyroscope System Using <inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula> Modulation Technology

This paper presents a digitalized gyroscope system using $\Sigma \Delta $ modulation on ADC (Analog to Digital Converter) and DAC (Digital to Analog Converter) sections. Both discrete ADC and DAC chips are replaced with these $\Sigma \Delta $ sections. The $\Sigma \Delta $ ADC technology can convert signals between analog and digital domain using analog modulators on the printed circuit board circuit with different amplifiers and matched capacity couples and digital backend processing in field programmable gate array (FPGA). While the $\Sigma \Delta $ ADC technology are easily realized in FPGA by signal processing algorithms the major sections of the digital system, such as auto gain control and phase-lock loop are also implemented in FPGA, which have provided the programmable flexibility of the whole system. The signal-to-noise ratio of power spectrum density (PSD) and stability in both $\Sigma \Delta $ ADC and $\Sigma \Delta $ DAC are analyzed, respectively. Considering the sections of the $\Sigma \Delta $ ADC and DAC woks in different clock domain, the frequency characteristics of each section should be analyzed. In the drive mode of the gyroscope, the force feedback is applied through the direct bitstream of the modulator. To evaluate the gyroscope vibration stability of the $\Sigma \Delta $ modulation-based system, the Leeson-model phase noise characteristics of the drive mode detection signal are in-depth theoretically calculated with different parameters, including the noise models and the circuit components, which has been experimentally validated by the measured PSD analysis. Finally, the performance evaluation of the whole gyroscope system is demonstrated by time-domain sampling and Allan variance analysis. The digitalized system achieved a scale factor of 94LSB/°/s, with a linearity of 83.1 ppm, noise of 00054°/s/ $\sqrt {\rm Hz}$ , bandwidth of 75 Hz, and the bias instability of 2.94°/h.

Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous

3D Stacked IC (3D-SIC) technology is becoming increasingly popular due to its improved design density and performance. However, single global clock distribution to a 3D-SIC can be very challenging and is far more prone to process and environmental non-idealities, which somewhat limits the scope of 3D-SICs. A possible solution to this problem is to perform inter-logic-layer communication in 3D-SICs using clock domain crossing (CDC) techniques. In this paper, we investigate the two classes of CDC techniques; the semi Quasi Delay Insensitive QDI-based asynchronous and loosely synchronous CDC. In particular, the paper explores the main challenges faced by these CDC techniques in utilizing through-silicon vias (TSVs). Representative designs from each technique are used for performing proof of concept electrical simulations. Our experimental results are expected to facilitate the 3D-SIC logic designers to choose the most appropriate CDC technique for a given design context. For example, one of the key findings of this paper is that although semi QDI-based asynchronous design provides an attractive solution because of its relaxed constraint on clock distribution network, but it has more timing overhead for TSV failures than the counterpart loosely synchronous design.

Eleven Ways to Boost Your Synchronizer

Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimum $V_{\rm TH}$ , over-provisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.

CMOS Layout Design and Performance Analysis for Synchronization Failures using 50nm Technology

The synchronizer is constrained such that its state does not change when a latching operation fails. Therefore, any failed latching attempts are automatically retried in the subsequent cycles. For this we simulates the 8 bit multiplier, 4 bit 16 state finite state machine, 16 slot 8 bit data first in first out register etc. In a multi clock system, synchronizers are required when on-chip data cross the clock domain boundaries which guard against synchronization failures but introduce latency in processing the asynchronous input. We use method that hides synchronization latency by overlapping it with computation cycles Synchronous logic is designed such that state bit transitions have sufficient time to propagate to subsequent flip-flops by the time of the following clock edge. If one flip-flop k becomes metastable and produces a transition whose clock-to-q delays is longer than expected, this transition may not have sufficient time to reach all destination flip-flops.

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques

Today's system-on-chip and distributed systems are commonly equipped with multiple clocks. The key challenge in designing such systems is that two situations have to be captured and evaluated in a single framework. The first is the heterogeneous control-oriented and data-oriented behaviors within one clock domain, and the second is the asynchronous communications between two clock domains. In this paper, we propose to use timed automata and synchronous dataflow to model the dynamic behaviors of the multiclock train-control system, and a multiprocessor architecture for the implementation from our model to the real system. Data-oriented behaviors are captured by synchronous dataflow, control-oriented behaviors are captured by timed automata, and asynchronous communications of the interclock domain can be modeled as an interface timed automaton or a synchronous dataflow module. The behaviors of synchronous dataflow are interpreted by some equivalent timed automata to maintain the semantic consistency of the mixed model. Then, various functional properties that are important to guarantee the correctness of the system can be simulated and verified within the framework. We apply the framework to the design of a control system described in the standard IEC 61 375 and several bugs are detected. The bugs in the standard have been fixed, and the new version has been implemented and used in the real-world subway communication control system.