Clock Delay Research Articles

FPGA implementation of curve fitting algorithm for image diffusion spectrum

Abstract In recent years, the application of image diffusion spectrum algorithm for high-concentration particle systems such as suspensions, coatings, emulsions, gels, etc. in multiple fields such as pharmaceuticals, energy, chemical industry, and food has become more and more extensive. Although the relevant technology has made significant progress at the algorithm level, the real-time and portability issues of the system are still the key factors restricting its application potential. The traditional image diffusion wave system needs to transfer the data to the host computer for processing after the image processing is completed, which has problems such as clock delay and large system volume. To this end, we proposed a fitting algorithm based on the image diffusion spectrum. By directly processing the data obtained in image processing in FPGA, clock delay is avoided and the miniaturization of the instrument is also achieved. Through comparative experiments, we can see that our algorithm can achieve the same processing effect on the host computer.

Formal timing analysis of gate-level digital circuits using model checking

Due to the continuous reduction in the transistors sizing ruled by the Moore’s law, digital devices have become smaller, and more complex resulting in an enormous rise in the delay variations. Therefore, there is a dire need of precise and rigorous timing analysis to overcome anomalies during the timing analysis. Timings of digital circuits can be verified using various simulation or static timing analysis (STA) based tools but they provide estimated results due to their inherent in-exhaustive nature or report timing paths corresponding to non-existent functional paths, respectively. Formal verification provides complete and sound analysis results and has widely been used for the functional verification of digital circuits but its application in the timing analysis domain is somewhat limited. We present a generic framework to perform formal timing analysis of digital circuits with the help of Uppaal model-checker. The given digital circuit along with its timing parameters in the form of state transition diagram are modeled using timed automata in the Uppaal model checker. Timing delays are calculated from corresponding technology parameters, and Quartus Prime Pro is used to obtain the information about the circuits’ paths. In order to make the analysis scalable, we also propose a novel path partitioning technique and compare its results with complete path analysis and traditional STA. The formal model is verified with the help of properties to assess the timing characteristics, like time period of a clock, critical path, and propagation delay of the considered circuit. Modeling and verification of ISCAS-85 and ISCAS-89 benchmark circuits is presented for illustration purposes.

Glucose restriction induces AMPK-SIRT1-mediated circadian clock gene Per expression and delays NSCLC progression

The rhythmic expression of the circadian clock is intimately linked to the health status of the body. Disturbed circadian clock rhythms might lead to a wide range of metabolic diseases and even cancers. Our previous study showed that glucose restriction was able to inhibit non-small cell lung cancer (NSCLC). In the current study, we found that glucose restriction enhanced apoptosis and cell growth delay in NSCLC cells. In addition, we used GEPIA database analysis to derive different effects of each circadian clock gene on lung cancer tissue. Among these circadian clock genes, Per (Period) is lowly expressed in cancer tissues and highly expressed in normal tissues. Moreover, the higher expression of Per in cancer patients has a better prognostic significance. Furthermore, we revealed that glucose restriction induced the expression of the circadian clock gene Per in NSCLC cells by upregulating SIRT1 (Sirtuin1) via activation of the energy response factor AMPK (AMP-activated protein kinase). Changes in Per expression following upregulation or downregulation of AMPK were consistent with AMPK expression. Additionally, a low-carbohydrate ketogenic diet significantly delayed tumor progression in a xenograft tumor model of severe combined immunodeficiency (SCID) mice. Meanwhile, the ketogenic diet increased the expression of AMPK, SIRT1 and Per in vivo. Besides, the ketogenic diet was found to restore the normal rhythmic level of Per by Zeitgeber Time (ZT) experiments. Taken these together, these results indicated a novel mechanism that glucose restriction induces AMPK-SIRT1 mediated circadian clock gene Per expression and delays NSCLC progression, which provided more evidence for glucose restriction as an adjuvant clinical therapeutic strategy in NSCLC.

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

Real-Time Water Level Monitoring Based on GNSS Dual-Antenna Attitude Measurement

Real-time and high-precision water level monitoring is crucial for the fields of hydrology, hydraulic engineering, and disaster prevention and control. The most prevalent method for measuring water level is through the use of water level gauges, which can be costly and have limited coverage. In recent years, Global Navigation Satellite System Reflectometry (GNSS-R) technology has emerged as a promising approach for water level monitoring due to its low cost and high coverage. However, a limitation of current GNSS-R technology is the extended time required to record signals, which hinders its potential for real-time application. This paper introduces a novel real-time water level monitoring method based on GNSS dual-antenna attitude measurement and develops a model to invert water level based on baseline vector. This method uses double-difference observations to eliminate errors caused by various factors, such as satellite and receiver clock, and ionospheric and tropospheric delay. To avoid the impact of detecting and correcting cycle slips during real-time operations, a single-epoch calculation method is introduced. In order to verify the stability and reliability of our method, field tests were carried out at Dongshahe Station in Beijing. We obtained water level data with a time resolution of 1 Hz through field experiments. Experimental data collected from 12 May to 8 June 2022 and from 4 July to 8 August 2022 showed good agreement with on-site water gauge measurements, with root mean square errors of 2.77 cm and 2.54 cm, respectively. Experimental results demonstrate that this method can achieve high-precision, high-temporal-resolution water level monitoring.

Design of Multiplier Circuit Using Carry Save Adder Based on Quantum-Dot Cell Automata

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

Model for Choosing the Shape Parameter in the Multiquadratic Radial Basis Function Interpolation of an Arbitrary Sine Wave and Its Application

In multiquadratic radial basis function (MQ-RBF) interpolation, shape parameters have a direct effect on the interpolation accuracy. The paper presents an MQ-RBF interpolation technique with optimized shape parameters for estimating the parameters of sine wave signals. At first, we assessed the impact of basic sinusoidal parameters on the MQ-RBF interpolation outcomes through numerical experiments. The results indicated that the angular frequency of a sine wave is a crucial determinant of the corresponding MQ-RBF interpolation shape parameters. A linear regression method was then used to establish the optimal parameter selection formula for a single-frequency sine wave, based on a large volume of experimental data. For multi-frequency sinusoidal signals, appropriate interpolation shape parameters were selected using the random walk algorithm to create datasets. These datasets were subsequently used to train several regression models, which were then evaluated and compared. Based on its operational cost and prediction accuracy, the random forest algorithm was chosen to establish the shape parameter selection model for multi-frequency sinusoidal signals. The inclusion of the Bayesian optimizer resulted in a highly accurate model. The establishment of this model enabled the adaptive selection of the corresponding shape parameters for any sine wave signal, providing a convenient means of selecting MQ-RBF interpolation shape parameters. Furthermore, the paper proposes an MQ-RBF interpolation subdivision least squares method that significantly improves the estimation accuracy of sine wave parameters. The practicality of the method was validated by successfully applying it in the calibration of the clock delay mismatch of a time-interleaved analog-to-digital converter system.

Dietary restriction and the transcription factor clock delay eye aging to extend lifespan in Drosophila Melanogaster

Many vital processes in the eye are under circadian regulation, and circadian dysfunction has emerged as a potential driver of eye aging. Dietary restriction is one of the most robust lifespan-extending therapies and amplifies circadian rhythms with age. Herein, we demonstrate that dietary restriction extends lifespan in Drosophila melanogaster by promoting circadian homeostatic processes that protect the visual system from age- and light-associated damage. Altering the positive limb core molecular clock transcription factor, CLOCK, or CLOCK-output genes, accelerates visual senescence, induces a systemic immune response, and shortens lifespan. Flies subjected to dietary restriction are protected from the lifespan-shortening effects of photoreceptor activation. Inversely, photoreceptor inactivation, achieved via mutating rhodopsin or housing flies in constant darkness, primarily extends the lifespan of flies reared on a high-nutrient diet. Our findings establish the eye as a diet-sensitive modulator of lifespan and indicates that vision is an antagonistically pleiotropic process that contributes to organismal aging.

Design of an efficient ALU blocks in quantum dot cellular automata (QCA)

Quantum-dot cellular automata (QCA) is a raising nanotechnology with the potential for quicker speed, smaller size and low power consumption than CMOS based technology. This paper proposes the design of functional blocks for Arithmetic Logic Unit (ALU) and for majority gate (MV) using certain unique QCA characteristics. Previous works were based on the conventional design and have different approaches when compared with QCA method. This paper helps to resolve the conventional method by converting all Boolean logics into a NAND and NOR based majority voter by fixing one of the inputs. The proposed work presents a significant amount of reduction in the cell count, area of the cell, and clock delay phase, compared to previous work in QCA. The experimental result shows a reduction in number of cells is by 35.40%, Area of cells (um2) by 15.88% and clock delay phase by 48.21%. Simulations indicate an appealing performance in terms of area, delay, and complexity. Simulation results are validated using the quantum-dot cellular automata (QCA) Designer 2.0.3 tool.

Two Novel One-Way Delay Clock Skew Estimators and Their Performances for the Fractional Gaussian Noise/Generalized Fractional Gaussian Noise Environment Applicable for the IEEE 1588v2 (PTP) Case

Papers in the literature dealing with the Ethernet network characterize packet delay variation (PDV) as a long-range dependence (LRD) process. The fractional Gaussian noise (fGn) or the generalized fractional Gaussian noise (gfGn) belong to the LRD process. The IEEE1588v2 is a two-way delay (TWD) protocol that uses the messages from the Forward (Master to Slave) and the Reverse (Slave to Master) paths. Suppose we have a significant difference between the PDV variances of the Forward and the Reverse paths. Thus, if we can use only the path with the lowest PDV variance (namely, only the one-way delay (OWD) technique), we might get a better clock skew performance from the mean square error (MSE) point of view compared with the traditional TWD method. This paper proposes two OWD clock skew estimators, one for the Forward path and one for the Reverse path applicable for the white-Gaussian, fGn and gfGn environment. Those OWD estimators do not depend on the unknown asymmetry between the fixed delays in the Forward and Reverse paths and nor on the clock offset between the Master and Slave. We also supply two closed-form approximated expressions for the MSE related to our new proposed OWD clock skew estimators. In addition, we supply some conditions, summarized in a table, guiding us whether we should use the OWD clock skew estimator for the Forward path or for the Reverse path, or just use the TWD algorithm. Simulation results confirm that our new proposed OWD clock skew estimators achieve better clock skew performances from the MSE point of view, compared with the TWD clock skew estimator recently proposed by the same authors and compared with two literature known OWD methods (the maximum likelihood and Kalman clock skew estimators).

Light sets the brain's daily clock by regional quickening and slowing of the molecular clockworks at dawn and dusk.

How daily clocks in the brain are set by light to local environmental time and encode the seasons is not fully understood. The suprachiasmatic nucleus (SCN) is a central circadian clock in mammals that orchestrates physiology and behavior in tune with daily and seasonal light cycles. Here, we have found that optogenetically simulated light input to explanted mouse SCN changes the waveform of the molecular clockworks from sinusoids in free-running conditions to highly asymmetrical shapes with accelerated synthetic (rising) phases and extended degradative (falling) phases marking clock advances and delays at simulated dawn and dusk. Daily waveform changes arise under ex vivo entrainment to simulated winter and summer photoperiods, and to non-24 hr periods. Ex vivo SCN imaging further suggests that acute waveform shifts are greatest in the ventrolateral SCN, while period effects are greatest in the dorsomedial SCN. Thus, circadian entrainment is encoded by SCN clock gene waveform changes that arise from spatiotemporally distinct intrinsic responses within the SCN neural network.

Evaluating and Enhancing Candidate Clocking Systems for CHIME/FRB VLBI Outriggers

Abstract As the Canadian Hydrogen Intensity Mapping Experiment (CHIME) has become the leading instrument for detecting Fast Radio Bursts (FRBs), CHIME/FRB Outriggers will use very-long-baseline interferometry (VLBI) to localize FRBs with milliarcsecond precision. The CHIME site uses a passive hydrogen maser frequency standard in order to minimize localization errors due to clock delay. However, not all outrigger stations will have access to a maser. This report presents techniques used to evaluate clocks for use at outrigger sites without a maser. More importantly, the resulting algorithm provides calibration methods for clocks that do not initially meet the stability requirements for VLBI, thus allowing CHIME/FRB Outriggers to remain true to the goal of having milliarcsecond precision.

QCA-based Hamming code circuit for nano communication network

Quantum-dot cellular automata (QCA) is one of the most promising technologies for designing digital circuits with high integration, ultra-low energy consumption, and high switching speed. The efficient implementation based on QCA has been verified in some nanocommunication code circuits. In this manuscript, a bottom-up method is adopted to design and implement novel 3–8 and 4–16 decoders. Based on the proposed structure, (7,4) and (15,11) Hamming codec circuits are implemented. The general design method of QCA Hamming code communication network is also given. For different generator matrices in Hamming codes, the proposed design only needs to modify the corresponding interconnection lines in the communication network without major adjustments to the circuit structure to achieve the same function. Compared with the Hamming code related designs in other studies, the proposed design has better hardware complexity. The proposed Hamming code circuit has a great performance improvement in terms of cell number, area, and clock delay. The above designs have been functionally verified by the QCADesigner.

Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

This work explores clock synchronization algorithms used to process timestamps from the IEEE 1588 precision time protocol (PTP). It focuses on the PTP-unaware network scenario, where the network nodes do not actively contribute to PTP’s operation. This scenario typically imposes a harsh environment for accurate clock distribution, primarily due to the packet delay variation experienced by PTP packets. In this context, it is essential to process the noisy PTP measurements using algorithms and strategies that consider the underlying clock and packet delay models. This work surveys some attractive algorithms and introduces an open-source analysis library that combines several of them for better performance. It also provides an unprecedented comparison of the algorithms based on datasets acquired from a sophisticated testbed composed of field-programmable gate arrays (FPGAs). The investigation provides insights regarding the synchronization performance under various scenarios of background traffic and oscillator stability.

A Design Methodology of Line Feedback Shift Registers With Quantum Cellular Automata

The quantum-dot cellular automata (QCA) present great promising advantages for emerging nano logic circuits. However, feedback design in QCA sequential circuit is often a big problem. Especially in line feedback shift registers (LFSR), each feedback loop consists of at least a modulo-2 adder and a trigger unit, which is hard to implement using the conventional methods. Given the importance of LFSR in communication systems, a design methodology with QCA is proposed in this work. At first, a new structure is presented to be used in every single feedback LFSR since it can make the feedback loop consume only one clock cycle of delay. Subsequently, quantitative criteria are presented to judge whether any multi-feedback LFSR can be directly designed using the proposed structure. LFSR that cannot satisfy the criteria are supposed to be transformed to their equivalent forms. We verify any LFSR can be transformed to the type of single feedback, according to the theorem of searching the monic and irreducible polynomials over Galois field GF (2). The step-by-step method of transforming multi-feedback into single feedback is given on the consideration of all kinds of cases. Further, two other simple transforming methods are presented to cope with the exponential growth of clock delay in the multi-to-single transforming method. The most remarkable advantage of this series of methods is to keep from introducing undesired bits into the payload data flowing in the sequential circuits.

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks

This paper presents UCloD, a novel random clock delay-based robust and scalable countermeasure against recently discovered remote power analysis (RPA) attacks. UCloD deploys very small clock delays (in the picosecond range) generated using the tapped delays lines (TDLs) to mitigate RPA attacks. UCloD provides the most robust countermeasures demonstrated thus far against RPA attacks. RPA attacks use delay sensors, such as Time to Digital Converters (TDC) or Ring Oscillators (ROs) to measure voltage fluctuations occurring in power delivery networks (PDNs) of Field Programmable Gate Arrays (FPGAs). These voltage fluctuations reveal secret information, such as secret keys of cryptographic circuits. The only countermeasure proposed thus far activates ROs to consume significant power and has managed to secure Advanced Encryption Standard (AES) circuits for up to 300,000 encryptions. Using TDLs available in FPGAs, UCloD randomly varies the clock to the cryptographic circuits under attack to induce noise in the adversary's delay sensor(s). We demonstrate correlation power analysis (referred to as CPA) attack resistance of UCloD AES implementations for up to one million encryptions. Compared to an unprotected AES circuit, UCloD implementations have minimal overheads (0.2% Slice LUT overhead and 4.8% Slice register overhead for Xilinx implementations and 0.5% LogicCells overhead for Lattice Semiconductor implementations).

A Robust and Efficient Fault-Resilient RadHard ADPLL

The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.

Deep time-delay reservoir computing: Dynamics and memory capacity.

The deep time-delay reservoir computing concept utilizes unidirectionally connected systems with time-delays for supervised learning. We present how the dynamical properties of a deep Ikeda-based reservoir are related to its memory capacity (MC) and how that can be used for optimization. In particular, we analyze bifurcations of the corresponding autonomous system and compute conditional Lyapunov exponents, which measure generalized synchronization between the input and the layer dynamics. We show how the MC is related to the systems' distance to bifurcations or magnitude of the conditional Lyapunov exponent. The interplay of different dynamical regimes leads to an adjustable distribution between the linear and nonlinear MC. Furthermore, numerical simulations show resonances between the clock cycle and delays of the layers in all degrees of MC. Contrary to MC losses in single-layer reservoirs, these resonances can boost separate degrees of MC and can be used, e.g., to design a system with maximum linear MC. Accordingly, we present two configurations that empower either high nonlinear MC or long time linear MC.

An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems

Due to the increasing interconnect delay caused by shrinking wiring dimensions, modern synchronous many-core systems are now facing critical issues. Particularly, the power budget to propagate high-frequency clock signals across the chip is limited. It becomes more challenging using conventional metallic interconnects to deliver a clock with low uncertainties across active dies. This article proposes a novel hybrid wireless-wired clock distribution network, which improves the performance of ON-chip clock distribution significantly. By using embedded wireless clock transmitter and receiver designs, because of the high fan-out feature of the wireless clock transmission, the overall clock delay, skew, and power have been reduced. The proposed hybrid clock distribution scheme is verified through a novel test circuit by using Arm Mali-G77 GPU as an example. Experimental results indicate that the proposed clock distribution network exhibits a significant global delay reduction of up to 28.8%. Also, for the best case scenario, a maximum of 46.7% and 17.7% reduction in clock skew and power consumption, are identified, respectively. Thus, our proposed approach offers a promising solution to clock distribution for many-core integrated circuits, especially for high-performance systems.

PPP models and performances from single- to quad-frequency BDS observations

Nowadays, China BeiDou Navigation Satellite System (BDS) has been developed well and provided global services with highly precise positioning, navigation and timing (PNT) as well as unique short-message communication, particularly global system (BDS-3) with higher precision multi-frequency signals. The precise point positioning (PPP) can provide the precise position, receiver clock, and zenith tropospheric delay (ZTD) with a stand-alone receiver compared to the traditional double differenced relative positioning mode, which has been widely used in PNT, geodesy, meteorology and so on. However, it has a lot of challenges for multi-frequency BDS PPP with different strategies and more unknown parameters. In this paper, the detailed PPP models using the single-, dual-, triple-, and quad-frequency BDS observations are presented and evaluated. Firstly, BDS system and PPP method are introduced. Secondly, the stochastic models of time delay bias in BDS-2/BDS-3 PPP including the neglection, random constant, random walk and white noise are presented. Then, three single-frequency, four dual-frequency, four triple-frequency and four quad-frequency BDS PPP models are provided. Finally, the BDS PPP models progress and performances including theoretical comparison of the models, positioning performances, precise time and frequency transfer, ZTD, inter-frequency bias (IFB) and differential code bias (DCB) are presented and evaluated as well as future challenges. The results show that the multi-frequency BDS observations will greatly improve the PPP performances.