Clock Cycle Latency Research Articles

A Low-Latency High-Order Arithmetic to Boolean Masking Conversion

Masking, an effective countermeasure against side-channel attacks, is commonly applied in modern cryptographic implementations. Considering cryptographic algorithms that utilize both Boolean and arithmetic masking, the conversion algorithm between arithmetic masking and Boolean masking is required. Conventional high-order arithmetic masking to Boolean masking conversion algorithms based on Boolean circuits suffer from performance overhead, especially in terms of hardware implementation. In this work, we analyze high latency for the conversion and propose an improved high-order A2B conversion algorithm. For the conversion of 16-bit variables, the hardware latency can be reduced by 47% in the best scenario. For the case study of second-order 32-bit conversion, the implementation results show that the improved scheme reduces the clock cycle latency by 42% in hardware and achieves a 30% speed performance improvement in software. Theoretically, a security proof of arbitrary order is provided for the proposed high-order A2B conversion. Experimental validations are performed to verify the second-order DPA resistance of second-order implementation. The Test Vector Leakage Assessment does not observe side-channel leakage for hardware and software implementations.

In-pixel AI for lossy data compression at source for X-ray detectors

Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. We compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50× compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70× compression, adds 30 clock cycle latency, and results in a similar area increase.

High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a nanotechnology-based circuit design technology to design efficient circuits. Serial–parallel multiplier (SPM) is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing SPM in QCA is discussed. Based on that architecture, an efficient 4-bit SPM is implemented in QCA. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is the first of its kind to implement SPM with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}} ^{2}$ </tex-math></inline-formula> with 25.25 clock cycle latency. To showcase, the scalability of a serial adder is also realized using the universal, scalable, and efficient clocking scheme.

An efficient hardware architecture based on an ensemble of deep learning models for COVID -19 prediction.

Deep learning models demonstrate superior performance in image classification problems. COVID-19 image classification is developed using single deep learning models. In this paper, an efficient hardware architecture based on an ensemble deep learning model is built to identify the COVID-19 using chest X-ray (CXR) records. Five deep learning models namely ResNet, fitness, IRCNN (Inception Recurrent Convolutional Neural Network), effectiveness, and Fitnet are ensembled for fine-tuning and enhancing the performance of the COVID-19 identification; these models are chosen as they individually perform better in other applications. Experimental analysis shows that the accuracy, precision, recall, and F1 for COVID-19 detection are 0.99,0.98,0.98, and 0.98 respectively. An application-specific hardware architecture incorporates the pipeline, parallel processing, reusability of computational resources by carefully exploiting the data flow and resource availability. The processing element (PE) and the CNN architecture are modeled using Verilog, simulated, and synthesized using cadence with Taiwan Semiconductor Manufacturing Co Ltd (TSMC) 90 nm tech file. The simulated results show a 40% reduction in the latency and number of clock cycles. The computations and power consumptions are minimized by designing the PE as a data-aware unit. Thus, the proposed architecture is best suited for Covid-19 prediction and diagnosis.

Stochastic Dividers for Low Latency Neural Networks

Due to the low complexity in arithmetic unit design, stochastic computing (SC) has attracted considerable interest to implement Artificial Neural Networks (ANNs) for resources-limited applications, because ANNs must usually perform a large number of arithmetic operations. To attain a high computation accuracy in an SC-based ANN, extended stochastic logic is utilized together with standard SC units and thus, a stochastic divider is required to perform the conversion between these logic representations. However, the conventional divider incurs in a large computation latency, so limits an SC implementation for ANNs used in applications needing high performance. Therefore, there is a need to design fast stochastic dividers for SC-based ANNs. Recent works (e.g., a binary searching and triple modular redundancy (BS-TMR) based stochastic divider) are targeting a reduction in computation latency, while keeping the same accuracy compared with the traditional design. However, this divider still requires <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> iterations to deal with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{N}$ </tex-math></inline-formula> -bit stochastic sequences, and thus the latency increases in proportion to the sequence length. In this paper, a decimal searching and TMR (DS-TMR) based stochastic divider is initially proposed to further reduce the computation latency; it only requires two iterations to calculate the quotient, so regardless of the sequence length. Moreover, a trade-off design between accuracy and hardware is also presented. An SC-based Multi-Layer Perceptron (MLP) is then considered to show the effectiveness of the proposed dividers over current designs. Results show that when utilizing the proposed dividers, the MLP achieves the lowest computation latency while keeping the same classification accuracy; although incurring in an area increase, the overhead due to the proposed dividers is low over the entire MLP. When using as combined metric for both hardware design and computation complexity the product of the implementation area, latency, power and number of clock cycles, the proposed designs are also shown to be superior to the SC-based MLPs (at the same level of accuracy) employing other dividers found in the technical literature as well as the commonly used 32-bit floating point implementation.

Using Universal Nand-nor-inverter Gate to Design D-latch and D Flip-flop in Quantum-dot Cellular Automata Nanotechnology

The process of reducing dimensions in CMOS technology and also making digital devices more portable, faces serious challenges such as increasing frequency and reducing power consumption. For this reason, scientists are looking for a solution such as replacing CMOS technology with other technologies including Quantum-dot Cellular Automata (QCA) technology and many researches have designed digital circuits by using QCA technology. Flip-flops are one of the main blocks in most digital circuits. In this paper, a D-type flip-flop (D-FF) is presented in QCA technology that a majority gate has been used in its feedback path to reset. The D-FF is designed by the proposed D Latch which is based on Nand-Nor-Inverter (NNI) and a new inverter gate that the proposed D latch has 24 cells and 0.5 clock cycle latency and 0.02 〖μm〗^2 area. The new inverter gate of the D-FF has output signal with high polarization level and lower area than previous inverters and the NNI gate of the D-FF is a universal gate. One of the applications of D-FFs with reset pin is the use in Phase-frequency detector (PFD). In the proposed scheme, a reset feature has been added to D-FF since the PFD structure can be designed. All of the proposed schemes are evaluated by the QCADesigner software and energy consumption simulations are estimated using QCAPro software for all proposed circuits.

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

SummaryCMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm2 area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm2 occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.

Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal

Today, due to the impossibility of further reducing the dimensions, electronic devices are faced with fundamental challenges in parameters such as speed, frequency, and power consumption for CMOS technology circuit. One solution is to replace CMOS technology with other technologies such as Quantum-dot Cellular Automata (QCA) technology. Extensive researches have been done for design digital circuits in QCA technology. Phase-frequency detector (PFD) is one of the main blocks in electrical and communication systems. In this paper, a structure is presented for a PFD in QCA technology for the first time. In the proposed structure, a D flip-flop (D-FF) with reset ability based on a new inverter gate is used. The new inverter gate of this D-FF compared to previous inverters, has output signal with high polarization level. Also, the proposed PFD has 199 cells, 0.22 μm2 occupied area and two clock cycles latency that is smaller compared with PFD which is designed with the conventional inverter.

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the phase-frequency detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new phase-frequency detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0.13 μm2 of an area and 1.5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$ Root and $N^{th}$ Power Computations

In this paper, we propose a low complexity architecture design methodology for fixed point root and power computations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and synthesized under the $TSMC 40$ -nm CMOS technology @ 1 GHz frequency. The synthesis results shows that the proposed ${ { N}}^{\text {th}}$ root computation saves 19.38% on chip area and 15.86% power consumption when compared with the state of the art architecture for root computation without compromising the computational accuracy. Similarly, the proposed ${ { N}}^{\text {th}}$ power computation saves 38% on chip area, 35.67% power consumption when compared with the state of the art power computation with out loss in accuracy. The proposed root and power computation designs save 8 clock cycle latency when compared with the state of the art implementations.

A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands

A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28-nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures.

Low‐latency median filter core for hardware implementation of 5 × 5 median filtering

This study presents hardware implementation of 5 × 5 median filter that uses a new low-latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is 394 MHz on the Xilinx Zynq FPGA device. The proposed LLMF core provides reduced clock cycle latency compared with the existing state-of-the-art median filter core architectures.

Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection

In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity value of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The defuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the smallest of maxima, and the largest of maxima. The defuzzification modules are interchangeable while the system runs using partial reconfiguration design methodology. System development was carried out using Vivado High-Level Synthesis, Vivado Design Suite, Vivado Simulator, and a set of Xilinx 7000 FPGA devices. Depending upon the speed grade of the device that is employed, the system can operate at a frequency range from 83 MHz to 125 MHz. Its peak performance is up to 58 high definition frames per second. A comparison of this system’s performance and its software counterpart shows a significant speedup in the magnitude of hundred thousand times.

English

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Improving hardware Trojan detection by retiming

Hardware Trojan horses (HTHs) are challenging threats to the security of silicon chips. A promising solution is path-delay fingerprinting for HTH detection. This paper presents trust-driven retiming(TDR), a synthesis approach to provide a circuit which can be analyzed more effectively by delay fingerprinting. To this end, TDR tries to reduce the maximum-delay path among all shortest paths crossing each node. We prove that HTH detection probability (HDP) is improved if delay fingerprinting is performed on shorter paths. Experimental results show that TDR can increase the HDP up to more than 90% at the cost of one clock cycle latency and a reasonable area overhead. The HDP tends to 100% if a 2% false alarm rate be acceptable.

Development of COTS ADC SEE Test System for the ATLAS LArCalorimeter Upgrade

Radiation-tolerant, high speed, high density and low power commercial off-the-shelf (COTS) analog-to-digital converters (ADCs) are planned to be used in the upgrade to the Liquid Argon (LAr) calorimeter front end (FE) trigger readout electronics. Total ionization dose (TID) and single event effect (SEE) are two important radiation effects which need to be characterized on COTS ADCs. In our initial TID test, Texas Instruments (TI) ADS5272 was identified to be the top performer after screening a total 17 COTS ADCs from different manufacturers with dynamic range and sampling rate meeting the requirements of the FE electronics. Another interesting feature of ADS5272 is its 6.5 clock cycles latency, which is the shortest among the 17 candidates. Based on the TID performance, we have designed a SEE evaluation system for ADS5272, which allows us to further assess its radiation tolerance. In this paper, we present a detailed design of ADS5272 SEE evaluation system and show the effectiveness of this system while evaluating ADS5272 SEE characteristics in multiple irradiation tests. According to TID and SEE test results, ADS5272 was chosen to be implemented in the full-size LAr Trigger Digitizer Board (LTDB) demonstrator, which will be installed on ATLAS calorimeter during the 2014 Long Shutdownmore » 1 (LS1).« less

New Cost-Effective Simplified Euclid’s Algorithm for Reed-Solomon Decoders

This paper proposes a cost-effective simplified Euclid's (SE) algorithm for Reed-Solomon decoders, which can replace the existing modified Euclid's (ME) algorithm. The new proposed SE algorithm, using new initial conditions and polynomials, can significantly reduce the computation complexity compared with the existing ME and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, since it has the least number of coefficients in the new initial conditions. Thus, the proposed SE architecture, consisting of only 3t basic cells, has the smallest area among the existing key solver blocks, where t means the error correction capability. In addition, the SE architecture requires only the latency of 2t clock cycles to solve the key equation without initial latency. The proposed RS decoder has been synthesized using the 0.18 μm Samsung cell library, and the gate count of the RS decoder, excluding FIFO memory, is only 40,136 for the (255, 239, 8) RS code.

Loop‐Reduction LLL Algorithm and Architecture for Lattice‐Reduction‐Aided MIMO Detection

We propose a loop‐reduction LLL (LR‐LLL) algorithm for lattice‐reduction‐aided (LRA) multi‐input multioutput (MIMO) detection. The LLL algorithm is an iterative algorithm that contains many check and process operations; however, the traditional LLL algorithm itself possesses a lot of redundant check operations. To solve this problem, we propose a look‐ahead check technique that not only reduces the complexity of the LLL algorithm but also produces the lattice‐reduced matrix which obeys the original LLL criterion. Simulation results show that the proposed LR‐LLL algorithm reduces the average number of loops or computation complexity. Besides, it also shortens the latency of clock cycles about 19.4%, 29.1%, and 46.1% for 4 × 4, 8 × 8, and 12 × 12 MIMO systems, respectively.

Simplified bit parallel systolic multipliers for special class of Galois field (2 m ) with testability

This study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate, one two-input XOR gate and two one-bit latches. This architecture is well suited to very large-scale integration implementation because of its regularity modular structure and unidirectional data flow. The proposed multipliers have clock cycle latency of (m+1). This architecture has a total reduction of m2 D-flip-flops compared to earlier bit parallel systolic multiplication architecture. As the finite-field multiplier is one of the complex blocks in cryptographic hardware and need secure testability to avoid unwanted access into the on-chip security blocks, the authors also introduce an on-chip testing scheme. The authors propose a test generation technique for detecting stuck-at fault (SAF), transition delay fault (TDF), stuck-open fault (SOF) and path delay faults (PDFs) at the gate and cell level in the systolic architecture. The authors also show that realistic sequential cell fault can be detected only by 12 single input change test vectors in the complete systolic multiplier over GF(2m). The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of an automatic test pattern generation tool. The complete systolic architecture is C-testable for SAF, TDF, SOF and PDF with only 12 constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF, TDF, SOF and PDF coverage.

Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of ${\rm GF}(2^{m})$

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ?m/L?, m is the word size and L is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.