Clock Cycle Latency Research Articles

FPGA implementations of low latency and high throughput 4×4 block texture coding processor for H.264/AVC

In this paper, low latency and high throughput texture coding architectures are proposed to realize the 4×4 integer/Hadamard transforms, the quantization (Q), and the inverse‐quantization (IQ) schemes for the H.264/AVC application. Based on matrix operations, the efficient fast two‐dimensional (2‐D) 4×4 transforms can be derived from the proposed one‐dimensional (1‐D) fast 4×4 transforms through matrix decompositions. The fast 2‐D 4×4 transform designs with the hardware sharing architecture can achieve high throughput and only need one clock cycle latency delay. The proposed cost‐effective and hardware sharing fast 2‐D 4×4 transform scheme doesn't require the transpose memory and can be applied to the 4CIF 4:2:0 video encoding. The hardware sharing architecture for both of the Q and the IQ is also developed for the low‐cost application. With Xilinx FPGA verifications, the proposed low‐cost 4×4 texture coding scheme, which can be applied to the CIF 4:2:0 30 frames/sec video encoding, can process up to 84 MHz with 90 k gate counts. Then the proposed high speed 4×4 texture coding design, which can be applied to the 4CIF 4:2:0 30 frames/ sec video encoding, can process up to 99 MHz with 135 k gate counts. Both of the two proposed texture coding architectures only require 4 clock cycles latency delay which is smaller than the traditional row‐column architectures do.

A Novel Envelope Detector for High-Frame Rate, High-Frequency Ultrasound Imaging

This paper proposes a novel design of envelope detectors capable of supporting a small animal cardiac imaging system requiring a temporal resolution of more than 150 frames per second. The proposed envelope detector adopts the quadrature demodulation and the lookup table (LUT) method to compute the magnitude of the complex baseband components of received echo signals. Because the direct use of the LUT method for a square root function is not feasible due to a large memory size, this paper presents a new LUT strategy dramatically reducing its size by using binary logarithmic number system (BLNS). Due to the nature of BLNS, the proposed design does not require an individual LOG-compression functional block. In the implementation using a field programmable gate array (FPGA), a total of 166.56 Kbytes memories were used for computing the magnitude of 16-bit in-phase and quadrature components instead of 4 Gbytes in the case of the direct use of the LUT method. The experimental results show that the proposed envelope detector is capable of generating LOG-compressed envelope data at every clock cycle after 32 clock cycle latency, and its maximum error is less than 0.5 (i.e., within the rounding error), compared with the arithmetic results of square root function and LOG compression.

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively

New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder

This paper proposes a new degree computationless modified Euclid (DCME) algorithm and its dedicated architecture for Reed-Solomon (RS) decoder. This architecture has low hardware complexity compared with conventional modified Euclid (ME) architectures, since it can completely remove the degree computation and comparison circuits. The architecture employing a systolic array requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t+2 basic cells has regularity and scalability since it uses only one processing element. Hence, the proposed DCME architecture provides the short latency and low-cost RS decoding. The DCME architecture has been synthesized using the 0.25-mum Faraday CMOS standard cell library and operates at 200 MHz. The gate count of the DCME architecture is 21 760. Hence, the RS decoder using the proposed DCME architecture can reduce the total gate count by at least 23% and the total latency to at least 10% compared with conventional ME decoders

HDD 읽기 채널용 6-bit 800 Msample/s DSDA 아날로그/디지털 변환기의 설계

본 논문에서는 하드디스크 드라이브 읽기 채널용 아날로그/디지털 변환기를 설계하였다. 본 회로는 고속 저에러율 비교 동작이 가능한 빠른 regenerative autozero 비교기에 기반을 두고 있고, 아키텍쳐에 Double Speed Dual ADC(DADA) 방식을 사용하여 전체 A/D 변환기의 속도를 효과적으로 향상시켰다. 또한 autozero 구조에 적합한 새로운 타입의 thermometer-to-binary 디코더를 사용하여 글리치를 제거하였고 기존의 구조를 보다 최적화시켰다. 이 ADC는 6-bit, 해상도, msample/s 최대 변환속도로 설계되었으며, 390mW 전력 소모와 한 클럭주기의 latency를 가진다. 설계에 0.65m CMOS 공정을 사용하였다. This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

A systolic architecture for computing inverses and divisions in finite fields GF(2/sup m/)

A new serial-in serial-out systolic array is presented for performing the element inversion in GF(2/sup m/) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation, It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m)-1 clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2/sup m/).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>