Clock Circuit Research Articles

The Drosophila circadian clock circuit is a nonhierarchical network of peptidergic oscillators.

The relatively simple Drosophila circadian clock circuit consists of 150 clock neurons that coordinate rhythmic behavior and physiology, which are generally classified based on neuroanatomical location. Transcriptional and connectomic studies have identified novel subdivisions of these clock neuron populations, and identified neuropeptides not previously known to be expressed in the fly clock circuit. An additional feature of fly clock neurons is daily axonal remodeling, first noted in small ventrolateral neurons, but more recently also found in additional clock neuron groups. These findings raise new questions about the functional roles of clock neuron subpopulations and daily remodeling of network architecture in regulating circadian behavior and physiology.

Circadian programming of the ellipsoid body sleep homeostat in Drosophila.

Homeostatic and circadian processes collaborate to appropriately time and consolidate sleep and wake. To understand how these processes are integrated, we scheduled brief sleep deprivation at different times of day in Drosophila and find elevated morning rebound compared to evening. These effects depend on discrete morning and evening clock neurons, independent of their roles in circadian locomotor activity. In the R5 ellipsoid body sleep homeostat, we identified elevated morning expression of activity dependent and presynaptic gene expression as well as the presynaptic protein BRUCHPILOT consistent with regulation by clock circuits. These neurons also display elevated calcium levels in response to sleep loss in the morning, but not the evening consistent with the observed time-dependent sleep rebound. These studies reveal the circuit and molecular mechanisms by which discrete circadian clock neurons program a homeostatic sleep center.

Cilia metasurfaces for electronically programmable microfluidic manipulation.

Cilial pumping is a powerful strategy used by biological organisms to control and manipulate fluids at the microscale. However, despite numerous recent advances in optically, magnetically and electrically driven actuation, development of an engineered cilial platform with the potential for applications has remained difficult to realize1-6. Here we report on active metasurfaces of electronically actuated artificial cilia that can create arbitrary flow patterns in liquids near a surface. We first create voltage-actuated cilia that generate non-reciprocal motions to drive surface flows at tens of microns per second at actuation voltages of 1 volt. We then show that a cilia unit cell can locally create a range of elemental flow geometries. By combining these unit cells, we create an active cilia metasurface that can generate and switch between any desired surface flow pattern. Finally, we integrate the cilia with a light-powered complementary metal-oxide-semiconductor (CMOS) clock circuit to demonstrate wireless operation. As a proof of concept, we use this circuit to output voltage pulses with various phase delays to demonstrate improved pumping efficiency using metachronal waves. These powerful results, demonstrated experimentally and confirmed using theoretical computations, illustrate a pathway towards fine-scale microfluidic manipulation, with applications from microfluidic pumping to microrobotic locomotion.

A Review on Design and Analysis of Low Power PLL for Digital Applications and Multiple Clocking Circuits

Abstract: A phase locked loop (PLL) is a basic element of many communication and instrumentation domain. This paper discusses the challenges in designing the low power PLL for multiple frequency output for digital applications. PLL is a key element providing clocking scheme in many electronic circuits raises the requirement of decreasing the power, with the advancement in CMOS technology. In this work, we provide review on low power PLL with good stability. Keywords: Phase-locked loop, CMOS, Clocking, low Power, Digital Applications, etc.

Computational Technologies for the Wearable Sports Training System Based on Sensor Acquisition

Aiming at the problems of long time-consuming and low precision in traditional training system, a wearable sports training system based on data mining is proposed and designed. According to the overall structure of the system, the hardware and software of the system are designed respectively. The hardware part is mainly composed of attitude measurement unit, power supply unit, main control unit, clock circuit, and reset circuit. The software part introduces the data mining method of mining sports training information data. The experimental results show that the system designed in this study effectively shortens the time-consuming time, improves the accuracy, and has certain advantages.

A Low-Power Passive UHF Tag With High-Precision Temperature Sensor for Human Body Application

Radio frequency identification (RFID) tags are widely used in various electronic devices due to their low cost, simple structure, and convenient data reading. This topic aims to study the key technologies of ultra-high frequency (UHF) RFID tags and high-precision temperature sensors, and how to reduce the power consumption of the temperature sensor and the overall circuits while maintaining minimal loss of performance. Combined with the biomedicine, an innovative high-precision human UHF RFID chip for body temperature monitoring is designed. In this study, a ring oscillator whose output frequency is linearly related to temperature is designed and proposed as a temperature-sensing circuit by innovatively combining auxiliary calibration technology. Then, a binary counter is used to count the pulses, and the temperature is ultimately calculated. We designed a relaxation oscillator independent of voltage and current. The various types of resistors were used to offset the temperature deviation. A current mirror array calibration circuit is used to calibrate the process angle deviation of the clock circuit with a self-calibration algorithm. This study mainly contributes to reducing power consumption and improving accuracy. The total power consumption of the RF/analog front-end and temperature sensor is 7.65 μW. The measurement error of the temperature sensor in the range of 0–60 °C is less than ±0.1%, and the accuracy of the output frequency of the clock circuit is ±2.5%.

Vasopressin Resets the Central Circadian Clock in a Manner Influenced by Sex and Vasoactive Intestinal Polypeptide Signaling

Background/Aims: Circadian rhythms in behavior and physiology are programmed by the suprachiasmatic nucleus (SCN) of the hypothalamus. A subset of SCN neurons produce the neuropeptide arginine vasopressin (AVP), but it remains unclear whether AVP signaling influences the SCN clock directly. Methods: Here, we test that AVP signaling acting through V1A and V1B receptors influences molecular rhythms in SCN neurons. V1 receptor agonists were applied ex vivo to PERIOD2::LUCIFERASE SCN slices, allowing for real-time monitoring of changes in molecular clock function. Results: V1A/B agonists reset the phase of the SCN molecular clock in a time-dependent manner, with larger magnitude responses by the female SCN. Further, we found evidence that both G_αq and G_αs signaling pathways interact with V1A/B-induced SCN resetting, and that this response requires vasoactive intestinal polypeptide (VIP) signaling. Conclusions: Collectively, this work indicates that AVP signaling resets SCN molecular rhythms in conjunction with VIP signaling and in a manner influenced by sex. This highlights the utility of studying clock function in both sexes and suggests that signal integration in central clock circuits regulates emergent properties important for the control of daily rhythms in behavior and physiology.

Design of thermometer based on STM32 and Bluetooth

This system uses temperature sensor DS18B20, Bluetooth module HC-05, microcontroller STM32f103ZET6, LCD display with 8080 port, RTC clock and alarm circuit to achieve portable temperature measurement rapidly. It can accurately measure the temperature and the deviation is kept within 0.5 degrees. The collected temperature data and the current time are displayed on the display screen. Send the collected temperature data at regular time and receive by APP mobile phone. When users want to get temperature data remotely on their phones, press the send button on the touch screen, press the up button and send the “wendu#” command to the cell phone APP to get the temperature data collected. When the temperature is over 37∘C, the four LED lights will always be on and LCD will show “Temperature is too high, please pay attention!” This design can not only realize the function of temperature measurement simply, but also optimize the display interface, modify the system time on the display interface to achieve the humanized function, which is convenient for daily portable use.

Sub-nanosecond synchronization implementation in pure Xilinx Kintex-7 FPGA

White Rabbit (WR) provides high-performance synchronization with sub-nanosecond accuracy and picoseconds precision, and it has been included in the new High Accuracy Default PTP Profile in the IEEE 1588-2019. As an open-source project, WR Precision Time Protocol (WR-PTP) core has been implemented in different FPGA platforms with dedicated clock circuits. This paper presents a novel approach to achieve the WR function in Xilinx Kintex-7 FPGA depending on the on-chip resource. This approach could achieve sub-nanosecond accuracy and tens of picoseconds precision, simplifying WR devices' hardware design and making it possible to port the WR PTP core to many mature hardware platforms.

A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator

A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for a wide range of temperature from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.

Regular Clocking based Emerging Technique in QCA Targeting Low Power Nano Circuit

ABSTRACT The transistor-based CMOS technology is facing tremendous physical challenges in nano-scale design. The Quantum-dot cellular automata (QCA) have attracted the research focus as aviable alternative to CMOS technology for future designs in the nano-scale. The cell interaction property helps in information propagation in QCA. The three-input majority gate, Inverter gate are the basic building blocks. The fabrication complexity can be optimised with coplanar and clock-based wire crossing techniques. Due to its low power feature, QCA has been experiencing significant power dissipation in its wire crossing and logic-driving cell, which needs special care. Moreover, various challenges to logic synthesis are associated with design automation and integration. Underlying metal wire crossing is another concern in the implementation of a regular clocking circuit. Extensive design proposals in QCA have been studied bypassing regular clocking and ends up with a question of proper fabrication or buildability. This research proposes an emerging technique to develop an efficient, scalable regular clocking scheme incorporating minimal metal wire crossing. The proposed clocking is employed for the cost-effective and power-efficient circuit design in both the sequential and the combinational approach. QCADesigner is used for circuit synthesis, whereas QCAPro and QCADesignerE have been utilised for energy dissipation analysis.

Gap junction protein Innexin2 modulates the period of free-running rhythms in Drosophila melanogaster

SummaryA neuronal circuit of ∼150 neurons modulates rhythmic activity-rest behavior of Drosophila melanogaster. While it is known that coherent ∼24-hr rhythms in locomotion are brought about when 7 distinct neuronal clusters function as a network due to chemical communication amongst them, there are no reports of communication via electrical synapses made up of gap junctions. Here, we report that gap junction proteins, Innexins play crucial roles in determining the intrinsic period of activity-rest rhythms in flies. We show the presence of Innexin2 in the ventral lateral neurons, wherein RNAi-based knockdown of its expression slows down the speed of activity-rest rhythm along with alterations in the oscillation of a core-clock protein PERIOD and the output molecule pigment dispersing factor. Specifically disrupting the channel-forming ability of Innexin2 causes period lengthening, suggesting that Innexin2 may function as hemichannels or gap junctions in the clock circuit.

Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

This paper characterizes the Single Event Effect (SEE) sensitivities of the Serializer/Deserializer (SerDes) module on the advanced 28 nm Xilinx Kintex-7 Field Programmable Gate Array (FPGA). A systematical SEE measurement method is proposed and implemented to evaluate the SEE sensitivity of the SerDes circuits. In our experiments, an extremely low Single Event Upset (SEU) Linear Energy Transfer (LET) threshold of the SerDes circuits was investigated, and both the recoverable and unrecoverable Single Event Functional Interrupts (SEFIs) were clearly distinguished and classified. In the experiments, it was found that the SEUs and recoverable SEFIs of the TX and RX in the same channel were closely related due to their shared clock and control circuits. Based on this detailed survey, a further discussion of the mechanisms of the SEU, recoverable SEFI, and unrecoverable SEFI is also provided. The SEE sensitivity of the high-speed SerDes circuits presented in this paper will promote the effective utilization of error mitigation strategies in order to control the risks of applications in radiation environments.

200-LB: Circadian Regulation of the MRTF-SRF Signaling Promotes Beige Adipocyte Development

The adipogenic progenitor transformation into mature adipocytes requires dissolution of intracellular actin cytoskeleton, and the cytoskeleton-MRTF/SRF signaling blocks adipogenesis. The circadian clock confers temporal control in metabolism, with tissue-intrinsic clock circuits contributing to metabolic homeostasis. In the current study, we identify a novel clock-MRTF/SRF regulatory axis that suppresses beige adipogenesis that is required for whole-body glucose metabolism. Key components of the cytoskeleton-MRTF/SRF signaling cascade display circadian oscillations in beige fat depot mediated by Bmal1 transcriptional activity. Genetic loss- or gain-of-functions of Bmal1 in adipogenic precursors markedly altered actin cytoskeleton organization, with silencing of Bmal1 inhibiting F-actin formation and MRTF/SRF activity whereas its forced expression augmenting actin architecture. Furthermore, we show that Bmal1 circadian control of the MRTF/SRF pathway drives beige thermogenic capacity in vivo. Prrx1-Cre-mediated beige fat-selective Bmal1 ablation induced beige depot browning with augmented mitochondrial metabolism, resulting in improved whole-body insulin sensitivity and resistance to obesity. Conversely, beige fat-specific overexpression of Bmal1 suppressed beige thermogenic program leading to impaired glucose tolerance and adipose expansion. Mechanistically, we show that Bmal1 deficiency enhanced beige precursor differentiation and thermogenic induction. Collectively, our findings uncover a temporal regulation of the cytoskeleton-MRTF/SRF signaling that modulates beige thermogenic capacity to maintain metabolic homeostasis. Disclosure X. Xiong: None. R. Liu: None. V. Yechoor: None. P. Saha: None. K. Ma: None. Funding National Institutes of Health (DK112794, DK097160-01); American Heart Association (17GRNT33370012)

CORRIGENDUM Systematic Cell placement in Quantum‐dot Cellular Automata Embedding Underlying Regular Clocking Circuit

IET Circuits, Devices & SystemsEarly View CORRIGENDUMOpen Access CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit This article corrects the following: CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit IET Circuits, Devices & Systems First Published online: May 25, 2021 CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit IET Circuits, Devices & Systems First Published online: May 25, 2021 Correction(s) for this article CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit IET Circuits, Devices & Systems First Published online: May 25, 2021 CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit IET Circuits, Devices & Systems First Published online: May 25, 2021 First published: 25 May 2021 https://doi.org/10.1049/cds2.12082AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat In [1], the following corrections should be noted. This work is sponsored by the Young Faculty Research Fellowship (YFRF) of Visvesvaraya Ph.D. scheme through the grant number MLA/MUM/GA/10(37)B. REFERENCE 1Bhowmik, D., et al.: Systematic cell placement in quantum-dot cellular automata embedding underlying regular clocking circuit. IET Circuits Dev. Syst. 15(2), 156– 167 (2021). https://doi.org/10.1049/cds2.12015Wiley Online LibraryWeb of Science®Google Scholar Early ViewOnline Version of Record before inclusion in an issue ReferencesRelatedInformation

Nanocircuits for Protection of the Cipher Information

While using side-channel attacks, cipher devices was defenseless to power and electromagnetic analysis attacks. These attacks are due to the use of low cost equipment. Currently, most of the cipher circuits are implemented on complementary metal-oxide-semiconductor. The disadvantage is the relationship between the data processing the curcuit to energy consumption. When processing the CMOS transistor logic "1" and the logic "0", through the transistor passes a different volume of current. If don't implement significant counteractions, it will allow another person to decrypt the key of the cipher module. A new logical approach to quantum-dot cellular automata and single-electron transistors is explored. The proposed approach has low power consumption and complicated clocking circuits. In theory and practice of cipher protection one of the key problems is the formation of binary pseudorandom sequences of maximum length of acceptable statistical characteristics. Generators of pseudorandom sequences usually based on linear shift registers with linear feedback. Here expanded the concept of linear shift register, believing that his every category (memory cell) can be in one of the states. Call registers are "generalized linear shift registers".

Design of intelligent invigilator system based on artificial vision

Aiming at the problems of high packet loss rate and low intelligent degree in the current video monitoring system for examination invigilation, an intelligent invigilator system design method based on artificial vision is proposed in this paper. The system design is divided into hardware and software parts, including a / D circuit, clock circuit, video frame cyclic error correction and coding circuit, program loading circuit and output interface circuit. The experimental results show that the system can effectively reduce the video packet loss in the process of invigilation, improve the visual coverage of the invigilator area, and the system is highly integrated and intelligent.

Design and Tradeoff Analysis of a Multi-Frequency Clocking Circuit Utilizing High-Speed Carry Chains on an FPGAs

본 논문에서는 디지털 회로의 동작상에서 발생하는 전자파 간섭(Electromagnetic Interference, EMI)를 감소시키기 위해서 FPGA 내부 구조에서 회로 자원으로 제공되는 고속의 캐리체인 (Carry chain) 회로를 사용하여 다중 주파수 클럭(multi-frequency clocking, MFC)을 생성하는 전략을 제안하고 이에 대한 성능 평가로 전자파감쇄 평가를 진행하였다. 제안된 MFC 회로는 전용의 고속 캐리 체인을 사용하며 지연회로 (Delay line)내에 상이한 수의 캐리체인 모듈 (CARRY4)을 할당함으로써 클럭 주파수를 적응적으로 변경한다. 제안된 구조는 Spartan 6 FPGA 상에서 구현하였으며, 실험 결과 제안된 구조를 통해서 만들어진 31.4 MHz의 MFC 회로에서 최대 32개의 클럭 주파수를 사용하여 전자파 노이즈를 10.41 dB 감소시킬 수 있음을 확인하였다. 그러나 주파수의 수가 증가함에 따라 성능상의 오버헤드가 증가하며 이에 대한 고려와 분석이 필요하다.

Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit

Quantum-dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

Programming the microcontroller in the real-time clock circuit when modeling the system in «Proteus»

A variant of programming the microcontroller and modeling the system in the «Proteus» RTC (Real Time Clock) circuit, together with LED matrices, is proposed. The practical significance of the work is the study of the simplest logic circuits in the AVR assembler language, for instance, a shift register, a decoder, a LED matrix, a real-time clock circuit and a seven-bit indicator, both individually and in a full-fledged system. This work can be used for teaching students and for laboratory work in distance learning.