CLB Slices Research Articles

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers.

Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables-RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

SHA-512 based Wireless Authentication Scheme for Smart Battery Management Systems

Modern cyber-physical systems depend on the battery backup systems for continuous service. Due to excessive wiring requirements, the traditional methods used for battery authentication cannot be applied to modern smart batteries, especially when they are composed of large number of cells. In this work, we proposed a wireless battery authentication scheme for use with the battery management system and the cells to prevent potential hardware attacks through the trojan cells. We designed a SHA-512 IP Core which operates at 157 MHz, and occupies 974 CLB slices and one block RAM on a Xilinx Artix-7 FPGA device. We integrated the SHA-516 module with a synthesizable CPU to be able to create a real-world test scenario and finally we verified the correct operation of an example authentication protocol through a wireless communication channel established with the use of two ESP8266 based WiFi modules.

High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

Design of FPGA Based Neural Network Controller for Earth Station Power System

Automation of generating hardware description language code of neural networks models can highly decrease time of implementation those networks into a digital devices, thus significant money savings. To implement the neural network into hardware design, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware. VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim® PE 6.6 simulator tool. Integration between MATLAB® and VHDL is used to save execution time of computation. The results shows that a good agreement between MATLAB and VHDL and a fast and flexible feed forward NN which is capable of dealing with floating point arithmetic operations; minimum number of CLB slices; and good speed of performance. FPGA synthesis results are obtained with view RTL schematic and technology schematic from Xilinix tool. Minimum number of utilized resources is obtained by using Xilinix VERTIX5.

Design of FPGA Based Neural Network Controller for Earth Station Power System

Automation of generating hardware description language code from neural networks models can highly decrease time of implementation those networks into a digital devices, thus significant money savings. To implement the neural network into hardware designer, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware. VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim ® PE 6.6 simulator tool. Integration between MATLAB ® and VHDL is used to save execution time of computation. The results shows that a good agreement between MATLAB and VHDL and a fast/flexible feed forward NN which is capable of dealing with floating point arithmetic operations; minimum number of CLB slices; and good speed of performance. FPGA synthesis results are obtained with view RTL schematic and technology schematic from Xilinix tool. Minimum number of utilized resources is obtained by using Xilinix VERTIX5.