class-E Zero-voltage Switching Research Articles

Load‐independent inverse class‐E ZVS inverter and its application to wireless power transfer systems

This paper proposes a load-independent inverse class-E zero-voltage switching (ZVS) inverter. The proposed inverter achieves the constant output current and the ZVS at any load resistance without any control. The waveforms and design equations of the proposed inverter are shown. Besides, a wireless-power-transfer system was implemented using the proposed inverter. The designed WPT system kept the constant output voltage and the ZVS against load variations, which denoted the effectiveness of the proposed inverter and validities of the analytical equations.

Analysis and Design of Choke Inductors for Switched-Mode Power Inverters

This paper presents the design, analytical estimation of power losses, and experimental measurement of choke inductors for switched-mode power inverters. The described approach is applicable to a wide variety of circuits such as Class-E inverters and converters. The expressions required to design the magnetic core in the choke inductor using the area–product ( $A_p$ ) method are given. The equations for the dc resistance, ac resistance at high frequencies, and dc and ac power losses are provided for the solid round winding wire. To validate the presented approach, an example class-E zero-voltage switching power inverter with practical specifications is considered. A core with air gap is selected to avoid core saturation in the choke inductor, which conducts dc current and a small ac current. The gapped core power loss density and power loss are estimated using Steinmetz empirical equation. It is shown that the winding power loss due to the dc current is dominant for the given design. A comparison between the area–product $A_p$ method and the preexisting core geometry coefficient $K_g$ method is presented. The measured magnitude of the inductor impedance has shown that the designed choke is useful up to ten times the switching frequency.

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna's 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3---60.7%.

A Class-E Power Amplifier Design Considering MOSFET Nonlinear Drain-to-Source and Nonlinear Gate-to-Drain Capacitances at Any Grading Coefficient

This paper presents theory and analysis for class-E power amplifier considering MOSFET nonlinear gate-to-drain and nonlinear drain-to-source capacitances at any grading coefficient of the MOSFET body junction diode. The nonlinearity degree of a MOSFET parasitic capacitance is determined by the grading coefficient. When the grading coefficient is not considered in design procedure, the switch voltage waveform of the class-E power amplifier does not satisfy the switching conditions, which results in a decrease of the power conversion efficiency. Therefore, the grading coefficient is an important parameter to satisfy the class-E zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions. The MOSFET gate-to-drain capacitance is highly nonlinear, and it is more nonlinear than drain-to-source capacitance for most MOSFETs. In some cases, the change in the gate-to-drain capacitance can be as large as 100 times. The results show that this nonlinearity affects the class-E power amplifier properties, such as switch voltage, power output capability, and maximum switch voltage. Therefore, it is necessary to consider the nonlinearity of the gate-to-drain capacitance, along with the drain-to-source capacitance. A design example at 4 MHz operating frequency is also given to describe the design procedure. The ZVS and ZDS conditions are achieved in the obtained switch voltage. The circuit simulation was performed using PSpice software. For verification of the presented theory, a class-E power amplifier is fabricated. The measured results are verified with simulation and theory results.

Analysis, Design, and Implementation of the Class-E ZVS Power Amplifier With MOSFET Nonlinear Drain-to-Source Parasitic Capacitance at any Grading Coefficient

In this paper, analytical expressions for waveforms and design relationships are derived for the class-E power amplifier with the MOSFET nonlinear drain-to-source parasitic capacitance under the subnominal operation, i.e., only zero-voltage switching (ZVS) condition, for any grading coefficient m of the MOSFET body junction diode and 50% duty ratio. Only the MOSFET nonlinear drain-to-source parasitic capacitance is used for the analysis of the class-E ZVS power amplifier, and its nonlinearity is determined by the grading coefficient m. The switch voltage waveform does not satisfy the class-E ZVS switching condition when only the linear shunt capacitance is considered. The grading coefficient m is used as an adjustment parameter that provides accurate design to satisfy the given output power and peak switch voltage simultaneously. Therefore, the grading coefficient m is the important parameter to satisfy the class-E ZVS condition and given design specifications, which is the most important result in this paper. Additionally, the output power capability and maximum operating frequency are affected by the grading coefficient m. The analytical expressions are obtained by considering the grading coefficient m as an adjustment parameter, which is validated by PSpice simulations and laboratory experiments. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which denotes the usefulness and effectiveness of our obtained analytical expressions.

Waveform Equations, Output Power, and Power Conversion Efficiency for Class-E Inverter Outside Nominal Operation

This paper presents analytical expressions for steady-state waveforms, output power, and power conversion efficiency for the class-E inverter outside the class-E zero-voltage switching and zero-derivative switching conditions. The analytical expressions in this paper include the MOSFET-body-diode effect. By carrying out PSpice simulations and circuit experiments, it is shown that the analytical predictions agree with the simulated and experimental results quantitatively, which indicates the validity of the analytical expressions. Additionally, the switching-pattern distribution maps are also given by using the analytical waveform equations.

Modeling and analysis of class-E zero-voltage switching amplifier at any grading coefficient and duty ratio

This paper introduces the class-E power amplifier with only the MOSFET nonlinear drain-to-source parasitic capacitance as a shunt capacitance for the class-E sub-nominal condition, i.e., zero-voltage-switching (ZVS) condition at any grading coefficient m of the MOSFET body junction diode and any duty ratio D. The obtained analytical expressions for waveforms and design equations show that the grading coefficient m and the duty ratio D can be used as the adjustment parameters, which increases the degree of the design freedom by two. The switch-voltage waveform does not satisfy the class-E switching condition when the grading coefficient m is different from the design specifications, which resulted in the power conversion efficiency degradation. On the other hand, the duty ratio D is determines the location of the class-E switching conditions. Therefore, the grading coefficient m and the duty ratio D are important parameters to satisfy the class-E sub-nominal condition. Although, the maximum operating frequency and the output power capability are affected by the duty ratio D, only the maximum operating frequency is affected by the grading coefficient m. We obtained the analytical expressions, which are validated by PSpice simulations and laboratory experiments that the grading coefficient m is considered. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which show the validity of our analytical expressions.