class-D Power Amplifier Research Articles

A low-complexity and high-frequency ASIC transceiver for an ultrasound imaging system.

This article presents a high-frequency application-specific integrated circuit (ASIC) transceiver for an ultrasound imaging system designed with a focus on low complexity. To simplify the design, it employs a conventional Class-D power amplifier structure for the transmitter (TX) and a resistive feedback transimpedance amplifier (TIA), which consists of a common-source amplifier followed by a source follower for the receiver (RX). Through careful optimization, the RX achieves a measured transimpedance gain of 90 dBΩ and an input-referred noise of 5.6 pA/√Hz at 30MHz while maintaining a wide bandwidth of up to 30MHz for both the TX and RX. The power consumption of the TX and RX is measured to be 7.767 mW and 2.5 mW, respectively. Further acoustic performance, assessed using an annular capacitive micromachined ultrasonic transducer (CMUT), showed a 1.78kPa peak pressure from a 20V pulser and confirmed the full bandwidth compatibility of the CMUT's bandwidth. The ASIC transceiver has been fabricated using a 0.18μm HV bipolar-CMOS-DMOS (BCD) process.

A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications.

Short-range Internet of Things (IoT) sensor nodes operating at 2.4 GHz must provide ubiquitous wireless sensor networks (WSNs) with energy-efficient, wide-range output power (POUT). They must also be fully integrated on a single chip for wireless body area networks (WBANs) and wireless personal area networks (WPANs) using low-power Bluetooth (BLE) and Zigbee standards. The proposed fully integrated transmitter (TX) utilizes a digitally controllable current-mode class-D (CMCD) power amplifier (PA) with a second harmonic distortion (HD2) suppression to reduce VCO pulling in an integrated system while meeting harmonic limit regulations. The CMCD PA is divided into 7-bit slices that can be reconfigured between differential and single-ended topologies. Duty cycle distortion compensation is performed for HD2 suppression, and an HD2 rejection filter and a modified C-L-C low-pass filter (LPF) reduce HD2 further. Implemented in a 28 nm CMOS process, the TX achieves a wide POUT range of from 12.1 to -31 dBm and provides a maximum efficiency of 39.8% while consuming 41.1 mW at 12.1 dBm POUT. The calibrated HD2 level is -82.2 dBc at 9.93 dBm POUT, resulting in a transmitter figure of merit (TX_FoM) of -97.52 dB. Higher-order harmonic levels remain below -41.2 dBm even at 12.1 dBm POUT, meeting regulatory requirements.

A Reconfigurable Bidirectional Wireless Power and Full-Duplex Data Transceiver IC for Wearable Biomedical Applications.

This paper presents a reconfigurable bidirectional wireless power and data transceiver (RB-WPDT) integrated circuit (IC) for wearable biomedical applications. The proposed transceiver can be reconfigured as a differential class-D power amplifier or a full-wave rectifier depending on the mode signal to facilitate power transfer between devices. Additionally, the RBWPDT system supports full-duplex (FD) data transmission via a single inductive link, enabling real-time control and monitoring between devices. The proposed FD method utilizes frequency shift-keying pulse-width modulation (FSK-PWM) for downlink and load shift-keying (LSK) for uplink, achieving simultaneous bidirectional data transmission by ensuring that the FSK-PWM downlink and LSK uplink data channels operate independently with minimal interference. The measured downlink and uplink data rates are 250 kb/s and 67 kb/s, respectively. The measured overall DC-to-DC efficiency is 49%, while the power delivered to the load (PDL) is 120 mW at a 5 mm distance. The proposed chip is fabricated using a 180-nm BCD CMOS process.

An Ultrasonic Transceiver for Non-Invasive Intracranial Pressure Sensing.

This paper presents a 9-mW ultrasonic through-transmission transceiver (TRX) for portable, non-invasive intracranial pressure (ICP) sensing. It employs two ultrasound transducers placed at the temporal bone windows to measure changes in the ultrasonic time-of-flight (ToF), based on which the skull expansion and the corresponding ICP waveform are derived. Key components include a high-efficiency Class-DE power amplifier (PA) with 95% efficiency and an output swing of 15.8 VPP, along with a successive approximation register (SAR) delay-locked loop (DLL)-based time-to-digital converter (TDC) with 29.8 ps resolution and 122 ns range. Other than electrical characterization, the sensor is validated through two demonstrations using a water tank setup and a human head phantom setup, respectively. It demonstrates a high correlation of R2 = 0.93 with a medical-grade invasive ICP sensor. The proposed system offers high accuracy, low power consumption, and reliable performance, making it a promising solution for real-time, portable, non-invasive ICP monitoring in various clinical settings.

A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil

This article presents a 6.78-MHz wireless power transfer (WPT) system with a differential class-D power amplifier (PA) for the transmitter (TX) and a delay-tuned rectifier for the receiver (RX). Besides the RX local voltage regulation, we propose a fully integrated TX global power regulation with wireless phase shift control without any extra off-chip components. Furthermore, the proposed system eliminates the feedback data-sensing coil used in prior arts, thus greatly improving the system integration level and reducing the circuit complexity. On the TX side, the global loop regulates the transmitted power through the duty cycle control of 1X/2X operation modes of the class-D PA to improve the system efficiency over a wide load range. On the RX side, we realize ac–dc power rectification and voltage regulation with a delay-tuned rectifier. The TX and RX chips fabricated in a standard 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m CMOS process used 3.3-V devices. Measured results show that the circuit can obtain a system efficiency improvement up to 14.2% at light load conditions, with the proposed wireless phase shift control regulating the TX global power. The peak end-to-end system efficiency is 77%, and the maximum output power is 0.9 W with a 3.3-V output voltage.

Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu m$ </tex-math></inline-formula> HV CMOS process. The total area of the PA is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~mm^{2}$ </tex-math></inline-formula> , where the DTG covers an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.066~mm^{2}$ </tex-math></inline-formula> . A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.

An Edge-Combining Frequency-Multiplying Class-D Power Amplifier

The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65nm CMOS prototype achieves output power and system efficiency of 22.3dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.

100 kHz Large-Signal Bandwidth GaN-Based 10 kVA Class-D Power Amplifier With 4.8 MHz Switching Frequency

Power amplifiers (PAs) are widely used, for example, to emulate the behavior of the power grid or electric machines under critical operating conditions, to measure the impedance of the power grid, or to generate specific impedance profiles in power-hardware-in-the-loop (P-HIL) tests. To accurately emulate dynamic effects and to characterize power electronic systems featuring wide-bandgap power semiconductors, PAs with very high output voltage quality and ever higher bandwidth (BW) at full output power are required, motivating the development of ultrahigh bandwidth power amplifiers (UHBW-PAs). While linear UHBW-PAs achieve very high signal fidelity and BW, they suffer from a tremendously bad efficiency, demanding large cooling effort and resulting in uneconomical operation, particular at high power levels and/or during long-term tests. Therefore, this article investigates possibilities for a switch-mode realization of UHBW-PAs with significantly higher efficiency and power density compared to existing solutions. There are two key concepts, namely series- and parallel-interleaving of multiple switching and/or converter cells, that allow to increase the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">effective</i> switching frequency relevant to output filtering without increasing the individual device switching frequency that determines the per device switching losses. This article analyzes comprehensively the advantages and disadvantages of a combination of series- and parallel-interleaving in terms of losses, volume and complexity scaling. Finally, a UHBW-PA with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {10}$</tex-math></inline-formula> kVA output power (single-phase), a nominal rms output voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {230}$</tex-math></inline-formula> V, a full-power BW of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {100}$</tex-math></inline-formula> kHz, very high output voltage quality (third and fifth harmonic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {&lt; 2.5}$</tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {&lt; 1.2}$</tex-math></inline-formula> V, respectively), an efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {&gt;95\%}$</tex-math></inline-formula> , a power density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {25}$</tex-math></inline-formula> kW/dm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {^{3}}$</tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {410}$</tex-math></inline-formula> W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {^{3}}$</tex-math></inline-formula> ), and a switching frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {4.8}$</tex-math></inline-formula> MHz is presented. A hardware demonstrator is built and extensive measurements verify the system performance and confirm the calculation from the initial analyses with loss models.

A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration

A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> . Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902–928 MHz while dissipating 210 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.

An automated system for nucleic acid extraction from formalin-fixed paraffin-embedded samples using high intensity focused ultrasound technology.

Formalin-fixed paraffin-embedded (FFPE) tissue samples are routinely used in prospective and retrospective studies. It is crucial to obtain high-quality nucleic acid (NA) from FFPE samples for downstream molecular analysis, such as quantitative polymerase chain reaction (PCR), Sanger sequencing, next-generation sequencing, and microarray, in both clinical diagnosis and basic research. The current NA extraction methods from FFPE samples using chemical solvent are tedious, environmentally unfriendly, and unamenable to automation or field deployment. We present a tool for NA extraction from FFPE samples using a high-intensity focused ultrasound (HIFU) technology. A cartridge strip containing reagents for FFPE sample deparaffinization and NA extraction and purification is operated by an automation tool consisting of a HIFU module, a liquid handling robot unit, and accessories including a thermal block and magnets. The HIFU module is a single concaved piezoelectric ceramic plate driven by a current-mode class-D power amplifier. Based on the ultrasonic cavitation effects, the HIFU module provides highly concentrated energy introducing paraffin emulsification and disintegration. The high quantity and quality of NA extracted using the reported system are evaluated by PCR and compared with the quantity and quality of NA extracted using the current standard methods.

A Real-Time Calibrated Adaptive-ZVS Class-D Power Amplifier for 6.78 MHz Wireless Power Transfer System

This brief presents a class-D power amplifier (PA) with an adaptive zero-voltage switching (A-ZVS) technique for 6.78 MHz resonant wireless power transfer (R-WPT) system. In R-WPT operation, the loading impedance of a PA can be varied by the process tolerance of the LC resonant components or WPT environments, such as the resonant topology, coupling coefficient, and loading condition of the receiver. In particular, the commonly used series-parallel resonant topology suffers from resonant point deviation of primary LC tank, resulting in hard switching of the PA. Consequently, efficiency degradation and electromagnetic interference can occur under multi-MHz operation. The proposed A-ZVS feedback loop calibrates the equivalent resonant capacitance in real-time to achieve ZVS by adjusting the loading impedance to be slightly inductive. The proposed PA was fully integrated except for one switched capacitor used as the tuning element and fabricated in a TSMC 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process. The measurement results demonstrated robust ZVS operation with a peak system efficiency of 52.7 % and an enhanced maximum transmitting power of 107 %.

A switched‐capacitor‐assisted wireless power transfer system with regulating TX power and fast global loop

Wireless power transfer systems demand a regulating transmitter (TX) for global loop control and also a regulating receiver (RX) for its local loop. This design broadens the TX output power range, by merging a switched capacitor (SC) circuit with only 3 switches and 1 flying capacitor to boost the output power of the Class-D power amplifier. In addition, the transmitting power can be regulated by the duty ratio of the SC, improving the end-to-end power transfer efficiency under different load conditions. Moreover, the system obtains fast load transient response, with the help of a light-to-heavy load transient enhancement scheme in the TX and the hysteretic control in the RX. Designed in a 0.18-μm BCD process, this work achieves 3.1 W maximum RX output power, 67.6% peak total efficiency, and 50 μs response time during the light-to-heavy load transient simulation.

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.

Adaptable Class-D Power Amplifier based Power Modulation and Data Transfer Technique for Biomedical Systems.

Class-D half and full-bridge power amplifiers (PA) finds their usefulness in wireless power transfer (WPT) blocks for a biomedical implant. This brief presents a 13.56-MHz wireless power transfer system using an adaptive PA structure and digital control scheme for providing sufficient power during downlink data transfer. This scheme prevents efficiency degradation due to amplitude modulation. Simultaneously changing PA structure and operating frequency gives a higher degree of freedom for power modulation. The transmitter and receiver sides were designed in the 0.18-μm CMOS process using 1.8 V and 5 V devices.

A 2.4 GHz Power Receiver Embedded With a Low-Power Transmitter and PCE of 53.8%, for Wireless Charging of IoT/Wearable Devices

This article presents a 2.4 GHz and high-efficiency wireless power receiver (Rx) integrated with a low-power transmitter (Tx) for wireless charging of the Internet-of-Things (IoT) or wearable devices. A single pole double throw (SPDT) circuit isolates the operation of the Rx from Tx, thereby offering the capability of sharing antenna between them. The Rx employs a high-efficiency radio frequency (RF)-dc converter, which is facilitated with threshold voltage cancellation technique for enhancing the efficiency, and adjustable internal impedance matching network to compensate the nonlinear behavior of the input impedance with respect to input power level. In addition, it includes a boost dc-dc converter to charge the storage element with a fixed voltage and current. The Tx utilizes a low-power phase-locked loop (PLL) and a class-D power amplifier (PA). Several techniques are adopted to achieve low power consumption. The chip is implemented in a 180 nm CMOS process with a die size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.3\,\,\mathrm {mm} \times 5\,\,\mathrm {mm}$ </tex-math></inline-formula> . The Rx shows the measured RF to dc maximum power conversion efficiency (PCE) of 53.8% at the input power level of 0 dBm. The Tx achieves a variable output power range of −10 to 10 dBm, while consumes 4 and 23 mA at 0 and 10 dBm output power, respectively.

A 6.78 MHz Single-Stage Wireless Power Transmitter Using a 3-Mode Zero-Voltage Switching Class-D PA

A 6.78 MHz single-stage transmitter (TX) using a reconfigurable regulating class-D power amplifier (PA) for wireless power transfer (WPT) applications is presented. Based on a 3-mode modulation scheme, the TX achieves power regulation and transmission with only one power stage. A discontinuous-conduction-mode (DCM) zero-voltage switching (ZVS) scheme is adopted to reduce switching loss. A control loop is set to regulate the output voltage of the WPT receiver (RX) by automatically adjusting the transmitting power. With dual-loop control and a proportional-integral (PI) compensation scheme, the loop achieves tight regulation and fast response. The controller is implemented digitally to benefit from the AirFuel <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> embedded Bluetooth communication link. The PA was fabricated with a high-voltage 0.35 μm CMOS process, and the digital controller with a standard 0.35 μm CMOS process, respectively. Measurement results show that the output voltage of the RX was correctly regulated to 11.7 V under a load change of 50mA to 500mA, and the WPT system could deliver a maximum power of 7.3 W to the RX over a distance of 4.0 cm, and achieved TX to RX peak efficiency of 57.3%.

Development of a Low-Cost, Portable NQR Spectrometer for RDX Explosives Detection

Nuclear quadrupole resonance (NQR) technology is a promising approach to detect so-called “minimum metal” landmines, as it can look directly for their explosive content. Conventional commercially available NQR devices, however, are large and expensive, and they require a transmitter power amplifier with a power generator, which is not suitable for outdoor use and mass production. Here we present a small and inexpensive portable device developed for detecting landmines using NQR. The device uses a field-programmable gate array (FPGA) and low-impedance transmission and reception circuits that include a dual supply class-D power amplifier powered by conventional batteries to ensure sufficient magnetic field excitation for mine detection. The pulse width modulation signals that are fed into the power amplifier have been designed to protect the low impedance transmit-receive switch circuit from the high voltage. The system has been tested successfully in the laboratory with 100g of explosive RDX at a distance of 10cm from the antenna, corresponding to a plausible anti-personal (AP) mine scenario. Detection was achieved with a signal to noise ratio (SNR) ~2 in 2/3 of the time that a previous prototype required (120 sec). Moreover, the new device can detect RDX explosives with a measurement time and SNR comparable to mine detectors built with commercial-off-the-shelf (COTS) components, but at lower cost and smaller form factor.

An Energy-Efficient Integration of a Digital Modulator and a Class-D Amplifier

Energy consumption is always a key feature in devices powered by electric accumulators. The power amplifier is the most energy-demanding module in mobile devices, portable appliances, static transceivers, and even nodes used in underwater acoustic networks. These devices incorporate a modulator, typically a pulse-width modulation (PWM) and a class-D power amplifier, for higher efficiency. We propose a technique to integrate the modulator of a transmitter and PW-modulator of a class-D amplifier to improve the overall efficiency of the system. This integrated set operates as an up-converter, phase modulator (PM), and binary phase-shift keying (BPSK) modulator under certain conditions. The theoretical concept is verified using Matlab and a model is designed and simulated in Simulink. For validation purposes, an electronic circuit is built and tested using Multisim. The results obtained by simulations and circuit implementation show that the proposed integrated system is an energy-efficient and cost-effective solution compared to conventional techniques.

Fourier Analysis of Signal Waveforms in An Ideal Concurrent Dual-Band Class-D Power Amplifier

Recently, a concurrent dual-band class-D power amplifier has been demonstrated to overcome the limitations of reduced efficiency in concurrent dual-band linear power amplifiers. However, the configuration could not be symbolically analyzed like its single-band counterpart due to the complicated nature of dual-band signals. This brief aims to provide a theoretical basis for idealized concurrent dual-band class-D operation. It applies an alternate representation of the sum of two sinusoids which helps the formulation of a technique to analytically extract the complex Fourier series coefficients of the current and voltage waveforms of the power amplifier. Expressions for output power and efficiency are derived, showing a theoretical drain efficiency of 100%. The theoretically obtained results are validated using observations from literature as well as independent Harmonic Balance simulation.

A Class-D Tri-Phasing CMOS Power Amplifier With an Extended Marchand-Balun Power Combiner

This article presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board. The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back off efficiency.Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by ON/OFF logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation.Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die.Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated Long Term Evolution (LTE) signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz.