Class AB Output Stage Research Articles

A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm

This brief presents a low-power forward and reverse body bias (FRBB) generator with body bias (BB) switches to dynamically set BB voltage. The reverse BB (RBB) P-well generator uses pulse frequency modulation (PFM)-based switching capacitor power converter to achieve low power consumption in a wide load current range of 1–30 $\mu ~\text{A}$ . The FBB adopts class-AB output stage and an over-current indicator to detect large body diode forward conduction leakage current. BB switch is introduced to dynamically configure the FRBB generated voltage. The proposed FRBB with BB switch is fabricated in a CMOS 40-nm triple well process, occupying an area of around 0.1 mm2. The 300k digital gates are used as the load for test. The measured active current for FBB and RBB are 13 and $5~\mu \text{A}$ , respectively.

A Low-Noise, Low-Power Amplifier With Current-Reused OTA for ECG Recordings.

This paper presents a low-power and low-noise capacitive-feedback amplifier with a current-reused OTA for ECG recordings. To improve the noise-power efficiency, the proposed OTA employs a current-reused architecture, which adopts an inverter-based differential input stage for low noise, and a class-AB output stage for large output range and high gm/I efficiency. The driving branch of the class-AB output stage is merged into the input stage to realize current reuse and reduce power consumption further. Fabricated in a 0.35-μm CMOS process, the amplifier consumes 160 nA from a 2-V supply, while achieving an input-referred noise of 2.05 μVrms, corresponding to a noise efficiency factor (NEF) of 2.26. The measured common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) exceed 65 dB and 70 dB, respectively. The total harmonic distortion (THD) is less than 1% with a 15-mVpp input at 20 Hz and the active area is 0.3 mm × 0.6 mm.

Low‐voltage fully differential difference transconductance amplifier

A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal-oxide-semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 μW. The FDDTA was designed in Cadence platform using 0.18 μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ $\mu \text{s}$ and −87 to −152.5 V/ $\mu \text{s}$ , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- $\mu \text{m}$ CMOS technology.

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage

A programmable gain amplifier (PGA) is presented, targeting amplifying input signal with high dynamic range and low noise. The proposed PGA adopts fully balanced differential difference amplifier (FBDDA) as main amplifier. A class-AB implementation of output stage is advantageous in order to achieve high current driving capability with very low quiescent power consumption. Combining resistor-feedback loop controlled by digital signal, the proposed PGA achieves a dB-linear gain range from 0 to 15dB with a gain step of 1dB. Compared with previous works, the theoretical analysis and measurement results prove that the proposed structure has lower noise. The circuit was designed and fabricated in SMIC 0.18µm 3.3V process, showing a gain error of less than 0.25dB, a third harmonic distortion (HD3) of better than −83dB and a thermal noise of 1.6 nv/Hz. The measurement results indicate that the PGA described here has a −3dB bandwidth of 387.5MHz at maximum gain of 15dB. The PGA occupies a chip area of 0.1mm2.

A Load-Adaptive Class-G Headphone Amplifier With Supply-Rejection Bandwidth Enhancement Technique

This paper presents a load-adaptive Class-G headphone amplifier to improve the power efficiency for different headphone impedances. For an impedance value, the amplifier utilizes two techniques, voltage rails selection and Class-G switching activity control, to reduce the power dissipation of the amplifier and the power loss of a Class-G power generator, respectively. In addition, a supply-rejection bandwidth enhancement technique for the Class-AB output stage is proposed to suppress the out-of-band noise by the Class-G supply rails switching. Compared with the conventional fixed 2-level Class-G amplifier, the integrated $0.18~\mu \text {m}$ CMOS amplifier improves the total-path efficiency to 37% from 31% (1.45 mA current can be saved from a 1.8 V supply) while delivering 5 mW into a $16~\Omega $ . The PSRR of the amplifier is 130 dB at 217 Hz and is still larger than 100 dB up to 20 kHz. Finally, the decoder and amplifier together achieve 108 dB DR and 95 dB SNDR with a $16~\Omega $ headphone load.

A 250-μW, 18-nV/rtHz current-feedback chopper instrumentation amplifier in 180-nm cmos for high-performance bio-potential sensing applications

This paper presents a low-power, high-performance current-feedback instrumentation amplifier (CFIA) for portable bio-potential sensing applications. Noise analysis is performed to assign an optimized current for the input stage of the amplifier. Analysis on selecting nested chopping frequencies is performed, further reducing 1/f noise and the residual offset. Enhanced power efficiency is achieved by sharing cascode branches and using a Class-AB output stage. Through these methods, a good balance between noise performance and other parameters such as output ripples and power consumption of the ripple reduction feedback loop (RRFL) is achieved. The amplifier is developed using a 1-poly 6-metal 0.18 μm CMOS process. Three gain stages with a gain-boosting input stage provide a low-frequency, open-loop gain >250 dB. When configured to a closed-loop gain of 60 dB, the amplifier achieves a noise voltage density of 18 $${\text{nV}}/\sqrt {{\text{H}}z}$$nV/Hz and a 1/f noise corner of 3 Hz. With a current of 75 μA and a supply voltage of 3.3 V, a CMRR of 110 dB and a PSRR of 120 dB are achieved, with an average input offset of about 6.5 μV. The amplifier achieves a state-of-art noise efficiency factor of 4.2. Practical application of the CFIA is demonstrated with an in vivo electrocardiogram detection.

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages.

Low power complementary metal‐oxide semiconductor class‐G audio amplifier with gradual power supply switching

The architecture, design and implementation of a low power complementary metal-oxide semiconductor (CMOS) class-G audio amplifier with gradual power-supply switching (GPSS) are presented. The proposed class-G amplifier output stage strategically uses the parallel connection of a class-AB output stage operating from smaller supplies (V DDL/V SSL), and a class-C output stage (with crossover from V SSL to V DDL) operating from higher supplies (V DDH/V SSH). GPSS is achieved using an efficient biasing scheme with level shifters. Moreover, the proposed biasing scheme in conjunction with negative feedback enables low distortion during the power-supply transition. Experimentally, the class-G amplifier prototype achieves a −82.5 dB THD + N, a peak load power of 50 mW and a quiescent power consumption of 350 μW. The proposed class-G amplifier was implemented in a standard CMOS 90 nm technology and occupies an active silicon area of 0.08 mm2.

Highly Efficient RF Transmitter Over Broad Average Power Range Using Multilevel Envelope-Tracking Power Amplifier

We present a highly efficient RF transmitter over broad average power range using a multilevel envelope-tracking power amplifier (ML-ET PA). The ML-ET PA delivers enhanced efficiency at a back-off power region for handset applications. The supply modulator consists of a linear regulator and a switching converter. The DC supply of the linear regulator is adjusted according to the average power of the envelope signal, and the power-supply-independent class-AB output stage is employed to avoid the crossover distortion generated by the different DC supply voltages. The switch current level is not optimally adjusted by itself following the power back-off level, because the DC supply voltages of the linear regulator and switching converter are different. For the optimum operation over the entire power region, the switch current level is adjusted by detecting the input envelope voltage level. For a 20-MHz long term evolution signal with a 7.5 dB peak-to-average power ratio, the proposed supply modulator delivers a peak voltage of 4.5 V to a 6.5 $\Omega$ load with a measured efficiency of 75.9%. The proposed ET PA delivers a power-added efficiency (PAE) of 40%, gain of 28.8 dB, evolved universal terrestrial radio access adjacent channel leakage ratio of $-$ 35.3 dBc, and error vector magnitude of 3.23% at an average output power of 27 dBm and an operating frequency of 1.71-GHz. At a 10 dB back-off point, the PAE is improved from 14.5% to 18.7% compared to the conventional ET PA.

Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- $\mu{\rm m}$ technology that occupies only $4.4\cdot 10^{-3} {\rm mm}^{2}$ , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 ${\rm mV}/\mu{\rm s}$ with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

Free class AB–AB Miller opamp with high current enhancement

A two-stage (Miller) operational amplifier (opamp) with both class AB input and output stages is introduced. It has a well-controlled quiescent current and generates dynamic output currents of up to a factor 45 times larger than the quiescent current. It uses very compact circuitry with small static power consumption in order to achieve class AB-AB operation and can operate with a low supply voltage. Experimental results of a test chip fabricated using 0.18 μm CMOS technology and simulations in 130, 90, 65 and 45 nm verify the proposed circuit.

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 μm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 μW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

This paper details a duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers. The duplex driver merges transmission, reception, and termination; eliminates hybrid and termination overhead; and enables adaptive echo cancellation and rail-to-rail full-duplex operation. Implemented in 28 nm CMOS, this GPHY driver passes the 1000BASE-T and 100BASE-TX compliance tests using a 2.5 V supply and meets the transmit specifications for the half-duplex 10BASE-T Ethernet using a 3.3 V supply.

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

SummaryA simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.

Low Voltage Power Efficient Tunable Shaper Circuit With Rail-To-Rail Output Range for the HYDE Detector at FAIR

This paper presents a low voltage, low power readout front-end system implemented in 130 nm CMOS technology. A conventional architecture that consists of charge sensitive amplifier, pole/zero cancellation and shaper has been used. The work focuses on the design of novel circuit topologies in low voltage environment minimizing the power consumption in modern deep submicron CMOS technologies. An operational amplifier with rail-to-rail output swing that uses a gain boosting technique and class-AB output stage without extra power consumption has been used for the shaper. The circuit combines excellent performances with simplicity of design and suitability for low voltage operation. The system is intended to work with silicon detectors for nuclear physics applications and is optimized to match an input capacitance of 10 pF. The system features a peaking time of 500 ns, a power dissipation of 1.57 mW/channel and an equivalent noise charge of 201 e-.

Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers

A high-performance buffer amplifier topology for liquid crystal display drivers is presented. The proposed amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested buffer can drive a 1000-pF capacitive load with a 5.7-V/μs slew-rate and a 0.71-μs settling time, while drawing 32-μA overall quiescent current from a 5-V power supply.

Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling

A differential temperature sensor for on-chip signal and DC power monitoring is presented for built-in testing and calibration applications. The amplifiers in the sensor are designed with class AB output stages to extend the dynamic range of the temperature/power measurements. Two high-gain amplification stages are used to achieve high sensitivity to temperature differences at points close to devices under test. Designed in 0.18 μm CMOS technology, the sensor has a simulated sensitivity that is tunable up to 210 mV/°C with a corresponding dynamic range of 13 °C. The sensor consumes 2.23 mW from a 1.8 V supply. A low-power version of the sensor was designed that consumes 1.125 mW from a 1.8 V supply, which has a peak sensitivity of 185.7 mV/°C over a 8 °C dynamic range.