class-AB OTA Research Articles

Low-power double linearization resistor and diode-connected MOS biasing based non-tailed class AB OTA

Low-power double linearization resistor and diode-connected MOS biasing based non-tailed class AB OTA

±0.15 V three‐stage bulk‐driven AB OTA with 36 MHzpF/µW and 55(V/µs)pF/µW small and large‐signal figures of merit

AbstractA three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

A Reference Voltage Circuit Applied in High Precision Delta-Sigma ADC

A novel reference voltage circuit design which is applied in high-precision Delta-Sigma ADC is implemented. The proposed reference circuit exploits a high-gain class-AB OTA as the error amplifier, which improves the transient response characteristics, ensures loop stability, and does not increase additional power consumption. The design and simulation of the proposed reference voltage circuit are fabricated by SMIC.18 CMOS technology. The simulation results manifest that the temperature coefficient of the bandgap reference is 6.825 ppm/°C in the temperature range from -40°C to 125°C. The transient response of the proposed reference circuit takes about 13 ns to reach the precision demanded by the reference voltage. The Σ-Δ modulator with the designed reference voltage circuit applied has an effective number of bits (ENOB) of 18.1 bits, a signal-to-noise-ratio (SNR) of 111.2 dB, and a signal-to-noise-plus-distortion (SNDR) of 110.9 dB at 1MHz sampling frequency and 625 Hz input signal.

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

An approach for the design of two-stage class-AB OTAs with sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1{\boldsymbol {\mu }}\text{A}$ </tex-math></inline-formula> current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Following this strategy, a class AB OTA was designed in a standard 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\boldsymbol {\mu }}\text{m}$ </tex-math></inline-formula> CMOS technology supplied from 1.6-V and experimentally tested. Measured GBW was 307 kHz with 980-nA DC current consumption while driving an output capacitance of 40 pF with an average slew rate of 96 V/ms.

Realisation of low voltage low power class AB OTA and its application in biquadratic filter

ABSTRACT In this paper, a new high-performance Class AB operational transconductance amplifier circuit is introduced. Based on flipped voltage follower technique, the proposed OTA showed a high DC gain of 41.33 dB with a unity gain frequency at 14 MHz, a wide dynamic range, a total harmonic distortion of −42.61 dB at 100 kHz and occupies only 28.64 x 20.61 µm2 chip area. Thereafter, a new single-input-multi-output (SIMO) transadmittance mode filter possessed by three multi-output OTAs and two capacitors is realised. The proposed filter can be achieved by all the standard filter functions without changing the circuit topology. The post-layout simulation results of the proposed OTA and biquadratic filter have been implemented with Cadence Virtuoso in TS18SL 0.18 µm technology Tower Jazz.

Two-stage class-AB OTA with improved specifications

Two-stage class-AB OTA with improved specifications

Low-power LDO Design of High-efficiency Class AB OTA Based on Adaptive Biasing

This design proposes a new low-dropout linear regulator (LDO) with low input voltage and low standby power consumption. A new type of adaptive bias circuit is proposed, which uses a high-efficiency class AB OTA based on class AB differential input stage and local common mode feedback (LCMFB), which not only increases the gain bandwidth product (GBW), but also improves current efficiency, in addition, a dynamic charging transistor (DCT) is used to enhance the transient characteristics of the circuit. The circuit design uses 0.18μm standard CMOS technology to achieve a stable output of 1.0V after the power supply voltage is adjusted from 1.2V, and the maximum output current is 100mA. The quiescent current is only 2.3μA at no-load, when the load current is converted from 1mA to 100mA within 1μs, the overcharge voltage is less than 130mV, and the full range of load current stability from 1mA to 100mA is achieved under the maximum 100pF load capacitor.

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only $0.7\mu \text{A}$ quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in $1\mu \text{s}$ the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figure-of-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

Ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate

An ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate is presented. Based on adaptive biasing and nonlinear current mirror techniques employed in a proposed symmetric current recycling structure, the proposed OTA not only achieves the maximum output current proportional to Vin8, but also has the symmetric positive and negative slew rates. Also, the proposed self-biasing output stage makes the slew rate unconstrained. Simulation results demonstrate that the slew rate of the proposed OTA is enhanced by 1500% over that of the conventional folded cascode counterpart with a little increased power, which is suitable for large capacitive load applications.

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

SummaryA scheme to achieve simultaneously extremely high slew‐rate improvement and avoiding open‐loop gain degradation in one‐stage super class AB op‐amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high‐output current enhancement factors at the expense of degrading the open‐loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew‐rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180‐nm complementary metal‐oxide semiconductor technology with open‐loop gain of 67 dB, a factor 2 improvement in GBW, and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley &amp; Sons, Ltd.

Fully Differential Class-AB OTA with Improved CMRR

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

High current efficiency class-AB OTA with high open loop gain and enhanced bandwidth

High current efficiency class-AB OTA with high open loop gain and enhanced bandwidth

Low power high-gain class-AB OTA with dynamic output current scaling

Low power high-gain class-AB OTA with dynamic output current scaling

Low-voltage micropower super class AB CMOS OTA

Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 µm CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.