class-AB Operational Transconductance Amplifier Research Articles

16.2-μW Super Class-AB OTA with current-reuse technique achieving 130.3-μA/μA FoM

In this paper, a single-stage Super Class-AB operational transconductance amplifier (OTA) using current reuse technique is presented. It is based on two scaled current mirrors located at the tail current nodes of input pairs, reusing the current through the cross-coupled input pairs by a current gain factor of α, and delivering new currents to the output branch, enhancing the overall transconductance (Gm) by a factor of (1+α). With adaptive biasing and local common mode feedback (LCMFB), slew rate (SR), open loop gain (AOL) and gain-bandwidth product (GBW) are improved. An prototype has been designed in TSMC 0.18-μm CMOS process. Post-simulation shows the positive and negative slew rate of 22V/μs and −38.3V/μs, respectively, a GBW of 3.72 MHz, a DC gain of 65.6 dB with a phase margin of 69.2° for a capacitive load of 70 pF. The proposed OTA consumes a total power of 16.2 μW under a 1.8V supply voltage.

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

Power-Efficient Single-Stage Class-AB OTA Based on Non-Linear Nested Current Mirrors

A novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gain-bandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.9~\mu \text{W}$ </tex-math></inline-formula> from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2. Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90° for a capacitive load of 160 pF.

Realisation of low voltage low power class AB OTA and its application in biquadratic filter

ABSTRACT In this paper, a new high-performance Class AB operational transconductance amplifier circuit is introduced. Based on flipped voltage follower technique, the proposed OTA showed a high DC gain of 41.33 dB with a unity gain frequency at 14 MHz, a wide dynamic range, a total harmonic distortion of −42.61 dB at 100 kHz and occupies only 28.64 x 20.61 µm2 chip area. Thereafter, a new single-input-multi-output (SIMO) transadmittance mode filter possessed by three multi-output OTAs and two capacitors is realised. The proposed filter can be achieved by all the standard filter functions without changing the circuit topology. The post-layout simulation results of the proposed OTA and biquadratic filter have been implemented with Cadence Virtuoso in TS18SL 0.18 µm technology Tower Jazz.

A capless NMOS low-dropout regulator with 15 ns transient response time

In this paper, a fast-transient capless NMOS low-dropout regulator (LDO) with low power consumption is proposed. The capacitor multiplier and Super Class-AB operational transconductance amplifier (OTA) with local common mode feedback structure (LCMFB) is employed in the proposed LDO, which not only consumes a small quiescent current but also greatly improves the transient response by increasing the loop bandwidth and charging/discharging current at the gate of the power transistor. Meanwhile, excellent line/load regulation is also achieved by the proposed LDO. The proposed capless LDO was implemented in 0.18 μm CMOS process and the post-layout simulation results show that the transient response of recovery time is only 15 ns, low quiescent current is 11 μA, and line regulation and load regulation are 0.61 mV/V and 7.58 μV/mA respectively.

An Ultra-Low-Voltage class-AB OTA exploiting local CMFB and Body-to-Gate interface

In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to increase the slew rate and attain class-AB behaviour, whereas two pseudo-resistors have been employed to increase the common mode rejection ratio (CMRR). The architecture has been extensively tested through Monte Carlo and PVT simulations, results show that the amplifier is very robust in terms of gain-bandwidth-product (GBW), power consumption and slew rate. A wide comparison against state-of-the-art has pointed out that best small-signal figures of merit are attained and good large-signal performance is guaranteed, also when worst-case slew rate is considered.

A Complex Band-Pass Filter for Low-Power and High-Performance Transceivers

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_Ω$ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/√Hz. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only 400 μA from a 1.2-V power supply.

A fast-transient low-dropout regulator (LDO) with Super Class-AB OTA

This paper presents a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA). The proposed structure not only achieve large charging/discharging current at the gate of power transistor but also a gain factor, which not only shows excellent transient performance but also ensures enough line/load regulation. Without adding addition circuit structure, the proposed LDO demonstrates a comprehensive improvement, including enhanced line/load regulation and transient performance, when compared with conventional counterpart, implemented in 0.18 μm CMOS technology, the proposed LDO shows a transient voltage variation of 53 mV at Vout for a load step of 10 μA-200 mA and possesses a line/load regulation of 1.25 mV/V and 100 μV/mA respectively.

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically. In the proposed method, layout effects are considered during the layout generation. Layout parasitics and geometry information are extracted from a new automated layout generator. In this method, the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as an optimization algorithm. In order to verify the performance of the proposed method, the design of three-stage operational amplifier (op-amp) and two-stage class-AB operational trans-conductance amplifier (OTA) in a 0.18µm process CMOS technology with 1.8 V supply voltage are presented. The simulation results indicate the efficiency of the proposed analog layout generation method.

Gain-Boosted Super Class AB OTAs Based on Nested Local Feedback

A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) of 236 V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.

Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain

This paper presents two low voltage high performance super class AB Operational Transconductance Amplifiers (OTAs) along with the second stage. The proposed OTA-I implements self cascode current mirrors (SCCMs) as the active load to provide high output swing. And the flipped voltage followers (FVFs) based adaptive biasing technique for the differential input stage to provide an additional current boosting and offers significantly improved slew rate and dynamic characteristics. Proposed OTA-II is the DTMOS implementation of proposed OTA-I suitable for low voltage operation. It utilizes the body effect and offers a more enhanced performance with minimized power consumption. The small-signal analysis shows the improvements achieved in dc gain and gain-bandwidth product (GBW). The second-order universal MISO filter realized using the proposed OTAs validates its competency. The simulation results are obtained using Mentor Graphics Eldospice tool with TSMC 0.18 ​μm technology. The proposed OTA-I (±0.75 ​V) and the proposed OTA-II (±0.5 ​V) provides dc gain as 105.66 ​dB and 108.15 ​dB with greatly improved average slew rate by factor 216 to 339 and enhanced GBW by factor 16 to 120 with reduced power dissipation as compared to conventional class A OTA. Besides, it also provides an improvement in the common-mode rejection ratio (CMRR). The figure of merit of proposed OTAs is 9621 [(MHz).pF/mW] and 50322[(V/μs).pF/mW] respectively for the load capacitor of 10 ​pF, and shows significant improvement compared to prior work. To authenticate the robustness of proposed OTAs, Monte Carlo and Corner analyses done with Process-Voltage-Temperature variations.

A 101 dB SNR fourth-order ΣΔ modulator for MEMS digital geophones

A fourth-order ΣΔ modulator (SDM) applied for micro-electro-mechanical systems (MEMS) digital geophones is presented in this paper. At the system stage, the proposed fourth-order SDM adopts a hybrid path technology including a feedforward path and a feedback path. At the design stage, a class AB operational transconductance amplifier with a gain bootstrap structure and chopper technique is employed in the first-stage integrator, which can achieve high DC gain, GBW, (Slew Rate) SR and reduce flicker noise, ensuring high (Signal-to-Noise Ratio) SNR for the proposed SDM. Meanwhile, other key modules are designed to meet basic requirements and achieve low power consumption at the same time. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and its final area is 3.09 mm2. When the sampling frequency of 512KHz and signal bandwidth of 2KHz are adopted, the measured results show that the proposed fourth-order SDM can achieve SNR of 101 dB and ENOB of 16.4 bits with less than 5mW power consumption, which meet the requirements of high dynamic range and low power in MEMS digital geophones.

Low quiescent current capacitor-less LDO regulator with high slew rate super class AB CMOS OTA

This paper presents a low quiescent current capacitor-less low-dropout regulator (LDO) with high slew rate super class AB CMOS operational transconductance amplifier (OTA). The OTA of this design is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth (GBW) product and slew rate (SR). LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. The design also uses dynamic charging transistor (DCT) to enhance the transient characteristics of the circuit. The presented LDO is fabricated in a 0.18 um standard CMOS process. The circuit consumes a quiescent current of 10 uA at no load, regulating the output at 1.0V with maximum output current of 100mA from a voltage supply of 1.2V. It achieves full range stability from 1mA to 100mA load current at a maximum 100pF load capacitor.

A High Slew-Rate Enhancement Class-AB Operational Transconductance Amplifier (OTA) for Switched-Capacitor (SC) Applications

This article presents a class-AB operational transconductance amplifier (OTA) with a high slew rate. The proposed class-AB OTA is applied with a slew-rate enhancement technique using an extremely low quiescent current. The additional current-reference common-mode feedback loop resolves the susceptibility to process, voltage, and temperature fluctuations resulting from slew-rate enhancement transistors. The proposed class-AB OTA is most widely used in block design, including, a switched-capacitor circuit, analog-to-digital converter, digital-to-analog converter, low-dropout regulator, and switched-capacitor DC-DC converters. In this study, performance was validated by applying the proposed class-AB OTA to a switched-capacitor delta-sigma modulator which requires high performance and high precision. The circuit was designed and simulated using a 0.18- $\mu \text{m}$ complementary metal-oxide semiconductor process.

84 dB DC‐gain two‐stage class‐AB OTA

Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

Class AB amplifier with enhanced slew rate and GBW

SummaryThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power‐efficient adaptive biasing circuit and a class AB current follower using the quasi‐floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5‐μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small‐signal performance.

High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

SummaryA novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

In this paper, a new two-stage class-AB operational trans-conductance amplifier (OTA) is proposed. Using active loads in the first stage and improved recycling structure, the effective trans-conductance of the first stage is increased. The nonlinear current mirrors boost the current of the second stage in the slewing mode, leading to the increase of the slew rate (SR). Exploiting the multi-path scheme and increasing the effective trans-conductance cause the OTA DC-gain to be enhanced. The proposed OTA has been fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The OTA exhibits 98 dB DC-gain and 21 MHz unity-gain bandwidth with a 100 pF capacitive load, consuming 3 mW from 1.8 V supply voltage.

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common-mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.