class-AB Operational Transconductance Amplifier Research Articles

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

SummaryA scheme to achieve simultaneously extremely high slew‐rate improvement and avoiding open‐loop gain degradation in one‐stage super class AB op‐amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high‐output current enhancement factors at the expense of degrading the open‐loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew‐rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180‐nm complementary metal‐oxide semiconductor technology with open‐loop gain of 67 dB, a factor 2 improvement in GBW, and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley & Sons, Ltd.

Two-stage class-AB OTA with enhanced DC gain and slew rate

ABSTRACTThis article proposes a new two-stage class-AB operational trans-conductance amplifier (OTA). In this OTA, the characteristics of class-AB are applied in both of the stages. By increasing the effective trans-conductance of the first stage, DC gain is improved. Non-linear current mirror boosts the current of the second stage; therefore, slew rate (SR) is increased. In order to verify the performance of the proposed OTA, some simulations are carried out in a 0.18-μm CMOS process in which the supply voltage is 1.8 V. The simulation results indicate 21-dB enhancement in DC gain and 2.7 times improvement in SR compared to its conventional counterpart. The post-layout and Monte Carlo simulations show the proposed OTA has better performance than the state-of-the art designs.

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits

This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 $\mu\text{m}$ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays

Due to its high resolution, small silicon area, and reasonable conversion rate, extended counting analog to digital conversion (EC-ADC) has become a competitive candidate for application in the readout circuits of high accuracy sensors. In this paper, an EC-ADC for large scale sensor arrays is proposed. At the system level, a double-sampling configuration for incremental $\Sigma\Delta$ modulators is proposed. By applying this configuration, the clock frequency of EC-ADC can be almost halved for the same conversion accuracy and rate. At the circuit level, the contribution of class-AB operational transconductance amplifier (OTA) structure to the low power design is analyzed and a class-AB OTA applicable for EC-ADC is developed. The proposed architecture has been implemented using a commercial 0.18 $\mu{\rm m}$ CMOS technology. Measured results show that a power consumption of less than 77 $\mu{\rm W}$ can be achieved at the conversion rate of 51.2 Ksamples/s and 12.2-bit accuracy respectively. The converter core occupies 0.044 ${\rm mm}^{2}$ .

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

SummaryThis paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.

A Power-Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using 0.18-μm CMOS technology.

A Power-Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 µW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using 0.18-µm CMOS technology.

Low power current sources for bioimpedance measurements: a comparison between Howland and OTA-based CMOS circuits

Abstract Multifrequency Electrical Bioimpedance (MEB) has been widely used as a non-invasive technique for characterizing tissues. Most MEB systems use wideband current sources for injecting current and instrumentation amplifiers for measuring the resultant potential difference. To be viable current sources should have intrinsically high output impedance for a very wide frequency range. Most contemporary current sources in MEB systems are based on the Howland circuit. The objective of this work is to compare the Mirrored Modified Howland Current Source (MMHCS) with three Operational Transconductance Amplifier (OTA) based voltage controlled current sources (i.e., class-A, class-AB and current conveyor). The results show that both current conveyor and class-AB OTA-based current sources have a wider output current frequency response and an output impedance of 226% larger than the MMHCS circuit at 1 MHz. The presented class-AB OTA circuit has a power consumption of 4.6 mW whereas current conveyor consumed 1.6 mW. However, the MMHCS circuit had a maximum total harmonic distortion of 0.5% over the input voltage from -0.5 to +0.5 V. The OTA-based current sources are going to be integrated in a semiconductor process. The results might be useful for cell impedance measurements and for very low power bioimpedance applications.

A low power 14 bit 51.2 kS/s double-sampling extended counting ADC with a class-AB OTA

A 14 bit 51.2 kS/s extended counting analog to digital converter (EC-ADC) is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilinear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier (OTA) is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 pJ/step.

A Wide-Swing Low-Noise Transconductance Amplifier and the Enabling of Large-Signal Handling Direct-Conversion Receivers

In this paper, the design of a wide-swing low-noise transconductance amplifier (LNTA) is presented in the context of passive mixer-based direct-conversion RF receivers, noting that the compression performance of such systems is limited by the initial voltage-to-current conversion. The proposed LNTA utilizes a stacked PMOS/NMOS common-gate configuration with its input common-mode voltage maintained by a class-AB operational transconductance amplifier (OTA). Linearization mechanisms and design procedures are explained both quantitatively and intuitively. Simulations of the LNTA at the typical corner, when ideally loaded, show an IIP3 + 32.8 dBm extrapolated at +12.5 dBm/-16.5 dBm CW blocking condition and an out-of-band 1-dB desensitization point of +22 dBm. These results are also shown to qualitatively agree with those extracted from an analytical model of the LNTA.

Digital 1 V 82 μW Pseudo-Two-Stage Class-AB OTA

A low power digital operational transconductance amplifier (OTA) was developed for low voltage switched capacitor applications. The OTA has a high slew rate (SR) and a large open loop gain with a differential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal (MIM) capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29 V/μs and the total power dissipation is only 82 μW.

Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current

High-Gain Class-AB OTA with Low Quiescent Current

High-performance operational transconductance amplifier (OTA) is designed for switched-capacitor applications. Without using a cascoded output stage, which limits the voltage swing, the output resistance is significantly increased for high DC gain by accurately controlling the output current. Also, the output stage has class-AB operation, so the overall power efficiency is improved. With significantly low quiescent current, the presented new OTA achieves higher DC gain than conventional OTAs. Theoretical analysis and HSPICE simulations prove the performance of the new OTA.

Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.

Low-power low-voltage differential class-AB OTAs for SC circuits

Two new differential class-AB operational transconductance amplifiers (OTAs) for SC circuits that operate with a supply voltage of less than two transistor threshold voltages are introduced. They make use of a new class-AB pseudodifferential pair to generate signal currents much larger than quiescent currents. Both OTAs have been designed to operate with a supply voltage of V/sub DD/=1.1 V, using a 0.35 /spl mu/m CMOS technology. Simulation results for a load capacitance (C/sub L/) of 1 pF show 15 MHz gain-bandwidth product with a quiescent power consumption of 10 /spl mu/W.

CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included.

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range

The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.