Circular Shift Register Research Articles

Pulse-Density-Modulated Microwave Generator Using Single-Flux-Quantum Circuits for Controlling Qubits

Superconducting qubits are generally controlled by irradiation with microwave pulses. We propose a 5-GHz-range microwave pulse generator based on pulse density modulation for controlling qubits using single-flux-quantum (SFQ) circuits. The proposed microwave pulse generator comprises a 100-GHz circular shift register and a band-pass filter (BPF). In this study, we investigated the relationship between the target envelope of the microwave amplitude and the SFQ pulse density based on the transfer function for the BPF and the frequency spectrum of an SFQ pulse. We implemented a 64-bit circular shift register and demonstrated its operation up to 68 GHz.

Implementation of encoder and decoder for low-density parity-check codes in continuous-variable quantum key distribution on a field programmable gate array

Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, ∼0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps decoding throughput was achieved, better than the theoretical key rate of prototype of CVQKD.

Automorphism groups of Walecki tournaments with zero and odd signatures

Walecki tournaments were defined by Alspach in 1966. They form a class of regular tournaments that posses a natural Hamilton directed cycle decomposition. It has been conjectured by Kelly in 1964 that every regular tournament possesses such a decomposition. Therefore Walecki tournaments speak in favor of the conjecture. A second interest in Walecki tournaments arises from the mapping between cycles of the complementing circular shift register and isomorphism classes of Walecki tournaments. The problem of enumerating non-isomorphic Walecki tournaments has not been solved to date. We characterize the arc structure of Walecki tournaments whose corresponding binary sequences have zero and odd signature. Automorphism groups are determined for zero signature Walecki tournaments and for odd signature Walecki tournaments with the zero signature Walecki subtournaments. Walecki tournaments possess a broad range of subtournaments isomorphic to some Walecki tournament. Subtournaments of odd signature Walecki tournaments induced by the outsets of the central vertex are proven to be either regular or almost regular.

Representative Scan Architecture

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.

Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform.

The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: a parallel array of fixed-point adder trees; circular shift registers to remove the need for accessing external memory components when selecting the input data for the adder trees; an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the input image. As a result, for an N × N image (N prime), the proposed approach can compute up to N(2) additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a 251×251 image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized just 2N + ⌈log(2) N⌉ + 1 and 2N + 3 ⌈log(2) N⌉ + B + 2 cycles, architectures that can compute the DPRT and its inverse in respectively, where B is the number of bits used to represent each input pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range >50 dB can be maintained up to 1 GHz, while keeping the DAC footprint small −0.035 mm $^{\mathrm {\mathbf {2}}}$ . Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm $^{\mathrm {\mathbf {2}}}$ . It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

A dual slope charge sampling analog front-end for a wireless neural recording system.

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.

All-optical circular shift register based on semiconductor optical amplifiers

We present a new and potentially integrable scheme to realize an all-optical circulating shift register consisting of a fiber-loop based optical buffer (OB) and an optical AND gate. The OB is implemented using semiconductor optical amplifier as a nonlinear element and the AND gate is realized by means of four wave mixing effect in a semiconductor optical amplifier. The operation of the shift register has been verified for a 10-bit input sequence at a sequence bit rate of 2.5 GHz and 10 GHz respectively. The simulation results show that \(\hbox {BER}=10^{-9}\) is achieved at optical signal-to-noise (OSNR) ratio of 16dB at the shift register output. The dependence of the output quality factor (\(Q\)-factor) on SOA parameters is also investigated and discussed.

All-Optical <formula formulatype="inline"><tex Notation="TeX">$N$</tex> </formula>-Bits Shift Register Exploiting a Ring Buffer Based on Semiconductor Optical Amplifier

The design and experimental characterization of an all-optical circular shift register are presented. The proposed scheme consists of a fiber loop optical buffer and a bit selecting circuit. A semiconductor optical amplifier (SOA) is used as an active element in the buffer structure, while the bit selecting circuit exploits Kerr effect in a highly nonlinear medium. The scheme is designed to store an N-bit sequence and to return the bits one by one at a lower clock rate, achieving proper circulating shift register functionality. Photonic integration is possible thanks to the presence of SOA in the buffer loop and to the absence of erbium-doped fiber amplifier-based feedbacks. Moreover, the increase in the number of bits to be stored does not increase the scheme complexity. Experimental validation is demonstrated for , and a signal-to-noise ratio per bit penalty equal to 5.6 dB is achieved at a bit error rate equal to with respect to the input sequence.

A Class of SIC Circuits: Theory and Application in BIST Design

This paper proposes a simplified algebraic model to present the complex configurations of single input change (SIC) circuits, and investigates the relationship between the SIC sequence and its generating circuit. Furthermore, several key properties of the studied sequence are provided and theoretically proved. Based on the above, we discover the commonness of different configurations of SIC circuits, and find the way to design the seed circuit at low overhead. To demonstrate our research results, a novel SIC circuit called seeded autonomous circular shift register (SACSR) circuit is presented. This new circuitry can automatically generate SIC sequences of more unique vectors. Finally, experimental results based on ISCAS85 Benchmark are provided to demonstrate the high performance of the proposed circuitry.

Classical and Quantum Operation Modes of the Reversible Josephson-Junction Logic Circuits

One of the most important features of the quantum computing circuits that distinguishes them from the traditional computational models is their full, physical and logical, reversibility at all stages of the calculations. This makes the large-scale architecture of potential quantum and classical reversible computers quite similar. The goal of this work is to analyze this similarity in the case of reversible superconducting logic circuits based on the recently suggested elementary gate, the nSQUID. Specifically, we present the results of numerical simulations and some limited measurements of a reversible 8-bit circular shift register fabricated at HYPRES, Inc., and working in the classical mode. The measured energy dissipation per bit operation per nSQUID is still about 20 times higher than the thermodynamic reversibility threshold of k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> TIn 2 at T ap 4 K. We also discuss qualitatively operation of the reversible circuits of galvan- ically-coupled nSQUIDs in the quantum mode which provides the basis for implementation of "flying" superconducting qubits. Such qubits have several attractive features for Josephson-junction quantum logic devices beyond the single- or two-qubit circuits.

Implementation and application of first-in first-out buffers

First-in, first-out (FIFO) buffers load and unload data using separate clocks that may be incoherent. We explore the application of FIFOs to circular shift registers, serial memory, and data re-clocking. We describe two different FIFO implementations in RSFQ. One employs classic handshaking using the Muller C-element. The other employs physical back-pressure based on repulsion of stored single flux quanta in a JTL. Both implementations use seven Josephson junctions, and a single bias resistor, per cell. The bias resistor can be reduced to an arbitrarily low value, thereby eliminating static power dissipation.

Negative-inductance SQUID as the basic element of reversible Josephson-junction circuits

It has been known for a long time that the thermodynamic limit k/sub B/Tln2 on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. However, explicit experimental demonstration of this is still lacking, and would be highly desirable both in its own right and in view of strong interest in inherently reversible quantum computation. In this work, we suggest a new gate, negative-inductance SQUID, that is suitable for the experimental demonstration of reversible information processing in Josephson-junction circuits, and present results of its theoretical analysis. We also describe layout-level designs of an individual nSQUID and an 8-cell circular shift register made of nSQUIDs.

Single flux quantum one-decimal-digit RNS adder

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μ W of power, and occupies an area of less than 2 mm 2 . Chips were fabricated at HYPRES, Inc. using 1 kA/cm 2 low- T c Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.

Experimental investigation of RSFQ circular shift registers

Abstract Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.

Timing jitter and bit errors in a 64-bit circular shift register

The bit-error rate of a 64-bit single-flux-quantum circular shift register, operating at a clock frequency of 10-16 GHz was measured. Error incidence depends on the values of the clock and data bias currents and on the clock frequency. Timing violation arising from thermal jitter is the dominant error mechanism. The jitter per JTL stage is estimated to be 290 fs based on the error rate data. This corresponds to a noise temperature of 8-9 K.

Low power parallel spread-spectrum correlator

Direct sequence spread spectrum (DSSS) transmissions require a despreading stage within the standard receiver block to recover the spread spectrum signal. For long spread spectrum codes, the correlation block can be a large portion of the receiver size, hence a considerable portion of the power consumption. The authors look at two power reduction alternatives for a parallel spread spectrum correlator, by analysing the algorithm and designing a baseline correlator and by investigating how to streamline the arithmetic operations in one case, and optimising the sample storage in the other. The two correlator designs are compared with a mix of analytical techniques and simulation data to determine the optimal correlator alternative for the DSSS application. The final analysis shows that the register file based correlator can reduce the power by over 30% for bus widths greater then 6 by using a structure which maintains the multi-bit data samples in a static area and by rotating the single bit coefficients around the data with a circular shift register.

High-speed operation of a 64-bit circular shift register

A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.