Circuit Reliability Research Articles

Generative Modeling of Semiconductor Devices for Statistical Circuit Simulation

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit’s behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device’s physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs.

A Novel Direct Current Circuit Breaker with a Gradually Increasing Counter-Current

A reliable and cost-effective mechanical direct current circuit breaker (DCCB) is a promising solution for DC interruption. However, the typical mechanical DCCB has difficulty in interrupting a rated current, because the high oscillating current superimposed on the rated current generates a steep current slope at current zero-crossing (CZC) points, which makes it difficult for the vacuum interrupter to extinguish the arc. The objective of this paper is to present a novel DCCB topology with a gradually increasing counter-current. It utilizes a full-controlled converter, a semi-controlled full bridge, and an LC oscillation branch to generate a gradually increasing counter-current, which is superimposed on any fault current and generates a smooth current slope at CZC points. The proposed DCCB topology is modeled with PSCAD, and the current slope and the initial transient interruption voltage (ITIV) at CZC are analyzed and compared with the typical mechanical DCCB. The results indicate that the current slope at CZC decreases by 57–84% in full-range current interruptions, and the ITIV can be reduced by the same extent. Additionally, the performance of the proposed DCCB is evaluated in a four-terminal HVDC system. A cost and performance comparison is conducted among the main topologies. The obtained results show that the proposed DCCB is a reliable solution for the multi-terminal HVDC system.

CMOS Based Voltage Reference Designs for Sub - 1V

This review paper presents an analysis of the most recent advancements in sub-1V voltage references, addressing the growing demand for ultra-low power consumption and high precision in modern integrated circuits (ICs). Voltage references are critical components in numerous applications, including IoT devices, wearable electronics, and energy-harvesting systems, where power efficiency and accuracy are paramount. It briefly discusses the challenges associated with designing voltage references at such low voltages, such as limited headroom, reduced noise margin, and process variations. Topics include high-order curvature compensation, modified differential pair configurations, and energy-efficient solutions for integrated energy harvesting. These advancements enhance precision and reliability in low-voltage circuits, paving the way for sustainable, low-power electronics and compact devices in the modern digital landscape. It emphasizes the importance of benchmarking different designs against criteria such as power consumption, line regulation, temperature stability, and supply voltage rejection ratio (PSRR). The paper include insights into the state-of-the-art sub-1V voltage reference designs, identification of design trade-offs, and recommendations for future research directions. It underscores the importance of continuous innovation in voltage reference design to address the evolving requirements of ultra-low power electronics. The study here is setting the stage for a detailed analysis of the latest developments in sub-1V voltage references.

Modelling reliability of reversible circuits with 2D second-order cellular automata

The cellular automaton is a widely known model of both reversible and irreversible computations. The family of reversible second-order cellular automata considered in this work is appropriate both for construction of logic gates and analysis of damage distribution. The quantities such as formal dimension of damage patterns can be used only for rough estimation of consequences of particular faults and numerical experiments are provided for illustration of some subtleties. Such analysis demonstrates high sensitivity to errors from defects, lack of synchronization and too short intervals between signals.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Design and hardware verification of photovoltaic converter based on adaptive P&O with snubber and BJT circuits

The efficient utilization of renewable energy is a key technology area of high domestic and international concern, and the research and development of DC–DC photovoltaic converters with high conversion efficiency is of great significance for improving performance and reducing the cost of solar power generation systems. In order to improve the conversion efficiency of solar energy, this paper proposes the design of a high-efficiency photovoltaic DC–DC converter with a non-isolated DC–DC converter as the object of the study. Solar power conversion is accomplished by designing a simple and reliable snubber circuit and a triode auxiliary circuit and tracking the maximum power point by combining the perturbation observation method with variable step size. The snubber circuit can effectively suppress the problems of pulse spikes and oscillations, and the triode auxiliary circuit prevents the reverse current and improves the switching speed, which reduces the switching loss and combines with the perturbation observation method with variable step size for fast and stable tracking of the maximum power point. In order to verify the feasibility of the converter, a 600 W prototype is designed. The experimental results show that using the snubber circuit reduces the pulse spike by 4.2 V and the overshoot is reduced by 4.3%. The maximum conversion efficiency is increased by 0.88% with the use of the transistor-assisted circuit, and the tracking efficiency of the MPPT is still stable under cloudy conditions. The maximum conversion efficiency of the prototype is finally measured to be up to 98.12%.

A Novel Method for Remaining Useful Life Prediction of RF Circuits Based on the Gated Recurrent Unit-Convolutional Neural Network Model.

The remaining useful life (RUL) prediction of RF circuits is an important tool for circuit reliability. Data-driven-based approaches do not require knowledge of the failure mechanism and reduce the dependence on knowledge of complex circuits, and thus can effectively realize RUL prediction. This manuscript proposes a novel RUL prediction method based on a gated recurrent unit-convolutional neural network (GRU-CNN). Firstly, the data are normalized to improve the efficiency of the algorithm; secondly, the degradation of the circuit is evaluated using the hybrid health score based on the Euclidean and Manhattan distances; then, the life cycle of the RF circuits is segmented based on the hybrid health scores; and finally, an RUL prediction is carried out for the circuits at each stage using the GRU-CNN model. The results show that the RMSE of the GRU-CNN model in the normal operation stage is only 3/5 of that of the GRU and CNN models, while the prediction uncertainty is minimized.

Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition

In wafer map defect pattern recognition, deep learning methods are predominantly used. These models autonomously learn features without explicit human intervention due to their black-box type network architectures. While preceding feature extraction and modality representation may seem neglected in deep learning for wafer map defect pattern recognition, we addressed this question by proposing an innovative approach. Our proposed method employs an antecedent feature learning module to create a more compact and informative hash modality representation from input wafer maps. The method exceeds in achieving high recall, crucial for identifying actual defective wafers as much as possible in semiconductor manufacturing, where defects can impact integrated circuit functionality and reliability. Smaller-sized hash modalities against larger wafer maps allow the same model to speed up the process and require fewer computational resources.

Optimized register level transfer mechanism for ASIC-based memscomputing

Micro-electromechanical system-based semiconductor sensor systems typically need a reliable on-chip analog readout circuit to identify and process changes in physical properties. To improve the mobility, robustness, reliability and performance (in terms of power consumption and speed) of the sensor system, the remaining parts of the post-processing logic, such as the digital data processor (or part of it), can also integrated into the chip. Cost and integration are always important considerations in both analog and digital designs, but they become even more important; the subsystem of data processing must be squeezed into a very small space near the structure of the micro-electromechanical system (MEMS) sensor. The paper introduces a new Buffalo-based register-transfer level (BRTL) method that aims to improve the efficiency and reliability of the system of digital data processing for MEMS sensor post-processing algorithm. Initially, the memcomputing system was designed with the needed functional processing elements. Then, a novel Buffalo-based register-transfer level design is modelled in the MEMS architecture. The digital data transmission process is performed to estimate the reliability of the proposed BRTL model. Finally, the performance of the proposed model can be validated.

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

Reducing two-level systems dissipations in 3D superconducting niobium resonators by atomic layer deposition and high temperature heat treatment

Superconducting qubits have arisen as a leading technology platform for quantum computing, which is on the verge of revolutionizing the world's calculation capacities. Nonetheless, the fabrication of computationally reliable qubit circuits requires increasing the quantum coherence lifetimes, which are predominantly limited by the dissipations of two-level system defects present in the thin superconducting film and the adjacent dielectric regions. In this paper, we demonstrate the reduction of two-level system losses in three-dimensional superconducting radio frequency niobium resonators by atomic layer deposition of a 10 nm aluminum oxide Al2O3 thin films, followed by a high vacuum heat treatment at 650 °C for few hours. By probing the effect of several heat treatments on Al2O3-coated niobium samples by x-ray photoelectron spectroscopy plus scanning and conventional high resolution transmission electron microscopy coupled with electron energy loss spectroscopy and energy dispersive spectroscopy, we witness a dissolution of niobium native oxides and the modification of the Al2O3-Nb interface, which correlates with the enhancement of the quality factor at low fields of two 1.3 GHz niobium cavities coated with 10 nm of Al2O3.

Machine-learning-based global optimization of microwave passives with variable-fidelity EM models and response features

Maximizing microwave passive component performance demands precise parameter tuning, particularly as modern circuits grow increasingly intricate. Yet, achieving this often requires a comprehensive approach due to their complex geometries and miniaturized structures. However, the computational burden of optimizing these components via full-wave electromagnetic (EM) simulations is substantial. EM analysis remains crucial for circuit reliability, but the expense of conducting rudimentary EM-driven global optimization by means of popular bio-inspired algorithms is impractical. Similarly, nonlinear system characteristics pose challenges for surrogate-assisted methods. This paper introduces an innovative technique leveraging variable-fidelity EM simulations and response feature technology within a kriging-based machine-learning framework for cost-effective global parameter tuning of microwave passives. The efficiency of this approach stems from performing most operations at the low-fidelity simulation level and regularizing the objective function landscape through the response feature method. The primary prediction tool is a co-kriging surrogate, while a particle swarm optimizer, guided by predicted objective function improvements, handles the search process. Rigorous validation demonstrates the proposed framework's competitive efficacy in design quality and computational cost, typically requiring only sixty high-fidelity EM analyses, juxtaposed with various state-of-the-art benchmark methods. These benchmarks encompass nature-inspired algorithms, gradient search, and machine learning techniques directly interacting with the circuit's frequency characteristics.

Cryogenic acoustic microscopy and evaulation of electronic components

Electronics operating at cryogenic temperatures are essential in fields like space exploration and particle physics. The Deep Underground Neutrino Experiment (DUNE), a next generation particle physics experiment, will rely on tens of thousands of custom designed application specific integrated circuits (ASICs) operating directly in liquid argon (87 K) for decades without repair or replacement. Ensuring circuit functional reliability throughout the duration of the experiment is mission critical. Both functional and nondestructive testing are employed to safeguard circuit quality and reliability. Part of this work involves the design, testing, and data analysis of a cryogenic acoustic microscope (CryoSAM) operating at 15 MHz. The CryoSAM is capable of interrogating ASICs at both room temperature (300 K) and in liquid nitrogen (77 K), identifying acoustic anomalies likely arising from thermal stress and manufacturing-related defects, using a powerful correlation analysis technique. These anomalies can lead to functional degradation and suboptimal electronic performance of the circuit sensors. Image analysis and correlations are used to compare differences seen before and after cryogenic temperature cycling. Data are reported that were collected at both room temperature and when cooled using liquid nitrogen. Designs and challenges of operating the instrument at cryogenic temperatures are also discussed.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

Optimal Photovoltaic Array Configuration under Non-Uniform Laser Beam Conditions for Laser Wireless Power Transmission

In a long-distance wireless power transmission system with a non-uniform distribution of laser irradiation, it will significantly reduce the output power of the photovoltaic array, resulting in a large amount of power loss in the system and a decrease in conversion efficiency. This paper proposes an efficient and reliable optimal circuit connection algorithm for the 5 × 5 scale photovoltaic array. Under the laser illumination of 300 W, a 20 m wireless power transmission experiment was performed on four 5 × 5 scale photovoltaic arrays. The results show a 56.49% increase in the maximum output power of the 5 × 5 scale photovoltaic array.

High gain and high-efficiency compact resonator antennas based on spoof surface plasmon polaritons

Abstract We proposed a high gain high-efficiency compact metallic resonator antenna operating at even-mode meander line spoof surface plasmon polaritons (MLSSPPs). The high radiation efficiency is caused by the bulk of fields crowded in lossless air near the antenna rather than in lossy dielectric as in conventional dielectric resonator antennas (DRAs). The proposed antenna also exhibits compact size because of its high effective refractive index. A reliable equivalent circuit model is proposed for the design of the resonator antenna with basic mode of half wavelength resonant mode. As an example, a meander-line SSPP antenna is designed, fabricated and measured. Both the simulated and measured results show the advantages of high efficiency and compact volume. In addition, the antenna achieves higher gain and wider relative bandwidth per wavelength cube volume compared with its counterparts. This method provides a good alternative for designing DRAs.

Using Memristor Element to Improve the Reliability of Digital Circuits

Memristor has been used as a filter stage to improve The reliability of digital circuits has been improved by using memristor. This element works as a filter stage to waive most of the glitches generated in prior stages. The proposed technique is applied to three different circuits to improve their reliability. Those circuits are: a chain of inverters represents a long path topology, c432 benchmark represents a short path circuit, c1908 benchmark represents a long path circuit. The memristor stage is connected between the last two stages of each output path of the circuit. The memristance of the memristor is changed using a certain parameter (x0), higher memristance means longer propagation delay and more glitches are attenuated. The experiment is run at different values of the memristance and the error probability is calculated at each value. The effect of this stage is studied by calculating the energy consumption and performance of the circuits with and without this stage. The Reliability-Energy-Performance trade-off relationship is found and introduced for each circuit, the results show that the reliability of the circuit is improved to the highest levels, when

A Low-Cost Triple-Node-Upset Self-Recovery Latch Design

As the CMOS process continues to decrease in size, the latch becomes increasingly vulnerable to the triple-node-upset (TNU), leading to a decrease in circuit reliability in harsh radiation environments. In this paper, a low-cost TNU self-recovery latch (LCTR) is proposed, which is based on one PMOS and two NMOS (1P2N) inverters and C-elements (CEs) forming a multi-level feedback loop. Due to the error interception function of these fundamental elements, the proposed latch completely realizes TNU self-recovery capability. Then the simulated tests are used for comparing the overhead of the LCTR latch and the other two typical TNU self-recoverable latches. The results reveal that the LCTR latch decreases power consumption by 56.98%, delay by 30.08%, area by 21.25% and PDP by 70.77%, respectively. Moreover, the LCTR latch is moderately sensitive to the variation of process, voltage and temperature (PVT).

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework’s efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities.

A robust radiation resistant SRAM cell for space and military applications

Many charged particles in space, including α-particles, neutrons, heavy ions, electrons, and photons, wreak havoc on the stability and reliability of memory circuits. In addition, these high-energy particles produce an ion track within the memory chip, which disrupts the storage bit. Standard 6T SRAM cannot withstand this upset condition. This paper presents a novel RRS-14T radiation-resistant SRAM memory cell with redundant nodes and a polar design to address the soft error issue. The performance of the proposed RRS-14T memory cell is compared to the performance of existing radiation-resistant memory cells, such as RHS-14T, RHMC-12T, NRHC-14T, QCCS-12T, HRRT-13T, and RHBD-13T. The RRS-14T cell protects against single and multiple-node disruptions. The read stability of the proposed RRS-14T memory cell is 2.83x/ 1.5x/ 2.10x/ 1.34x/ 3.38x/ 1.68x greater than the existing RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. Moreover, 1.08x/ 1.27x/ 1.06x/ 1.05x/ 1.16x/ 1.07x larger write trip voltage than RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. In addition, the write access time, hold power, and critical charge are enhanced when the supply voltage is at 1 V.