Circuit Timing Research Articles

A Perturbative Stochastic Galerkin Method for the Uncertainty Quantification of Linear Circuits

This paper presents an iterative and decoupled perturbative stochastic Galerkin (SG) method for the variability analysis of stochastic linear circuits with a large number of uncertain parameters. State-of-the-art implementations of polynomial chaos expansion and SG projection produce a large deterministic circuit that is fully coupled, thus becoming cumbersome to implement and inefficient to solve when the number of random parameters is large. In a perturbative approach, component variability is interpreted as a perturbation of its nominal value. The relaxation of the resulting equations and the application of a SG method lead to a decoupled system of equations, corresponding to a modified equivalent circuit in which each stochastic component is replaced by the nominal element equipped with a parallel current source accounting for the effect of variability. The solution of the perturbation problem is carried out in an iterative manner by suitably updating the equivalent current sources by means of Jacobi- or Gauss-Seidel strategies, until convergence is reached. A sparse implementation allows avoiding the refinement of negligible coefficients, yielding further efficiency improvement. Moreover, for time-invariant circuits, the iterations are effectively performed in post-processing after characterizing the circuit in time or frequency domain by means of a limited number of simulations. Several application examples are used to illustrate the proposed technique and highlight its performance and computational advantages.

Restoring Stephan Von Huene's Tap Dancer: Finding Logic within Integrated Circuits

ABSTRACT Stephan von Huene is recognized for his acoustical sculptures that combine movement and sound with the flip of a switch. This paper will focus on his Tap Dancer (1967) composed of cropped legs in pants and shoes on a wooden base that perform a 30-second tap dance at regular intervals. The movement and sound are controlled by integrated circuit boards wired to valves, a vacuum and recycled musical components. The condition of the wiring and circuitry is critical to allow the performance, which is intended to be random by way of an erasable programmable read-only memory (EPROM) and timing circuit. Von Huene's sculptures have conservation issues when exhibited and plugged in for action. Challenges arose during the exhibition of Tap Dancer at the J. Paul Getty Museum in Los Angeles leading to conservation interventions including the adaptation of EPROM data to a solid-state controller. After exhibition at the Getty, the temporary solutions were replaced with a full restoration of the original circuit boards repairing wiring or damaged chips as needed. The history of Tap Dancer has shown that with the desire to exhibit von Huene's works as intended, the endurance of their structures is inevitably at risk.

FATIMA — FAst TIMing Array for DESPEC at FAIR

The components, working principle and characteristics of FATIMA (FAst TIMing Array), a fast-timing detector system for DESPEC at FAIR, are described. The core system includes 36 LaBr3(Ce) scintillator detectors, a mounting frame for the DESPEC station and a VME-based fast-timing data acquisition system. The current electronic timing circuit is based on V812 constant fraction discriminators and V1290 time-to-digital converters. Gamma-ray energies are measured using V1751 digitisers. Characteristics of the core FATIMA system including efficiency, energy, and coincidence resolving time, as well as limitations, are discussed on the basis of test measurements performed in the S4 cave at GSI, Germany. The coincidence γ-γ time resolution for the prompt 60Co cascade is determined to be ∼320 ps full width at half maximum. The total full energy peak efficiency at 1 MeV for the 36 detector array in the DESPEC setup is 2.9%. The energy-dependent prompt response centroid curve with the current CFD/TDC combination is shown to be smooth; the centroid shift method can be applied for the measurement of half-lives below 200 ps. An overview of applications of the FATIMA detectors as an ancilliary system in combination with other detector arrays during recent years is given. Data on the operation of the detectors in the presence of magnetic fields are presented.

A self-adaptive blanking time circuit for fast IGBT de-saturation short-circuit protection

A self-adaptive blanking time circuit for fast IGBT de-saturation short-circuit protection

Study of the Dynamic Characteristics of Some Circuit Optimization Strategies

The work explores the possibility of a significant reduction in processor time required to optimize analog circuits. For this, we can reformulate and generalize the problem of chain optimization based on the approaches of optimal control theory. The analog circuit design process is formulated as a dynamic controlled system. A special control vector has been defined to redistribute the computational cost between circuit analysis and parametric optimization. This redistribution significantly reduces CPU time. The task of designing a circuit for the minimum processor time can be formulated as a classical optimal control problem while minimizing some functional. The introduction of the concept of the Lyapunov function of a controlled dynamic system made it possible to use it to analyse the main characteristics of the design process. An analysis of the behaviour of a special function, which is a combination of the Lyapunov function and its time derivative, made it possible to compare various design strategies and select the best ones that are executed in minimal CPU time.

Selection of Control Vector Switching Points for Circuit Optimization

The process of optimizing the circuit is formulated as a controlled dynamic system. A special control vector has been defined to redistribute the computational cost between circuit analysis and parametric optimization. This redistribution will help solve the task of optimizing the circuit for minimum CPU time. In this case, the task of optimizing the circuit with minimal CPU time can be formulated as the classical optimal control problem for minimizing some functional. The concept of the Lyapunov function of a controlled dynamic system is used to analyze the main characteristics of the design process. An analysis of the Lyapunov function and its time derivative makes it possible to predict the optimal structure of the control vector for constructing an optimal or quasi-optimal circuit design algorithm. The results are based on the previously discovered effect of accelerating the design process. In this case, the optimal structure of the control vector is determined, which minimizes processor time.

Development of an Arduino Based Electric Cooker Timer System

The emerging trend in the world of semiconductor integration has brought about so many opportunities in the area of microcontrollers. This paper deals with the design and implementation of a microcontroller-based timer for home appliances using an Arduino microcontroller. This system is developed for the users to predetermine the time of operation of any home appliances using the electric cooker for implementation. The system is majorly comprised of the power supply unit, microcontroller unit, timer circuits and LCD display. The user can set any of the time given in the timer switch using keypad. The settings are stored in the microcontroller and the details are displayed in the LCD display. The appliance is controlled to run for the particular period set by the timer switch. The timer switch automatically makes the appliance off once the period is over. This system has been designed to be efficient, reliable and reduce energy wastage.

An egg timing circuit.

An egg timing circuit.

Simulation of Simplified BSPD Deploying Timer Circuit for a Prototype Formula Electric Car

Now-a-days electrical vehicles are growing faster than the vehicles fuelled with conventional energy resources and are expected to replace conventional vehicles in near future,owing to its zilch emissions and environmental friendly. Albeit the electrical vehicles are contributing to the reduction in air and noise pollution, few technical issues have to be resolved for its improved performance. Currently electric vehicle is turned off automatically, for avoiding the shaft failure due to the twisting load acting on the shaft, while operator applies the accelerator pedal and brake pedal simultaneously. Hence, an attempt had been made to delay the system getting turned off by introducing a timer circuit in BSPD (Brake System Plausibility Device). The functioning of simplified BSPD with timer circuit was simulated using the Proteus software andthe outcome of the simulated results is presented in waveforms, which confirms the proper functioning of the circuit. A PCB for engaging the shutdown circuitwas also developed to control the electric vehicle’s powertrain. The hardware implementation of the simulated circuit had been carried out and the real time working of the circuit was verified.

Internal short circuit detection in Li-ion batteries using supervised machine learning

With the proliferation of Li-ion batteries in smart phones, safety is the main concern and an on-line detection of battery faults is much wanting. Internal short circuit is a very critical issue that is often ascribed to be a cause of many accidents involving Li-ion batteries. A novel method that can detect the Internal short circuit in real time based on an advanced machine leaning approach, is proposed. Based on an equivalent electric circuit model, a set of features encompassing the physics of Li-ion cell with short circuit fault are identified and extracted from each charge-discharge cycle. The training feature set is generated with and without an external short-circuit resistance across the battery terminals. To emulate a real user scenario, internal short is induced by mechanical abuse. The testing feature set is generated from the battery charge-discharge data before and after the abuse. A random forest classifier is trained with the training feature set. The fault detection accuracy for the testing dataset is found to be more than 97%. The proposed algorithm does not interfere with the normal usage of the device, and the trained model can be implemented in any device for online fault detection.

The Application of EEG Mu Rhythm Measures to Neurophysiological Research in Stuttering.

Deficits in basal ganglia-based inhibitory and timing circuits along with sensorimotor internal modeling mechanisms are thought to underlie stuttering. However, much remains to be learned regarding the precise manner how these deficits contribute to disrupting both speech and cognitive functions in those who stutter. Herein, we examine the suitability of electroencephalographic (EEG) mu rhythms for addressing these deficits. We review some previous findings of mu rhythm activity differentiating stuttering from non-stuttering individuals and present some new preliminary findings capturing stuttering-related deficits in working memory. Mu rhythms are characterized by spectral peaks in alpha (8–13 Hz) and beta (14–25 Hz) frequency bands (mu-alpha and mu-beta). They emanate from premotor/motor regions and are influenced by basal ganglia and sensorimotor function. More specifically, alpha peaks (mu-alpha) are sensitive to basal ganglia-based inhibitory signals and sensory-to-motor feedback. Beta peaks (mu-beta) are sensitive to changes in timing and capture motor-to-sensory (i.e., forward model) projections. Observing simultaneous changes in mu-alpha and mu-beta across the time-course of specific events provides a rich window for observing neurophysiological deficits associated with stuttering in both speech and cognitive tasks and can provide a better understanding of the functional relationship between these stuttering symptoms. We review how independent component analysis (ICA) can extract mu rhythms from raw EEG signals in speech production tasks, such that changes in alpha and beta power are mapped to myogenic activity from articulators. We review findings from speech production and auditory discrimination tasks demonstrating that mu-alpha and mu-beta are highly sensitive to capturing sensorimotor and basal ganglia deficits associated with stuttering with high temporal precision. Novel findings from a non-word repetition (working memory) task are also included. They show reduced mu-alpha suppression in a stuttering group compared to a typically fluent group. Finally, we review current limitations and directions for future research.

Finding Small and Large $k$-Clique Instances on a Quantum Computer

Algorithms for triangle-finding, the smallest nontrivial instance of the k-clique problem, have been proposed for quantum computers. Still, those algorithms assume the use of fixed access time quantum RAM (QRAM). We present a practical gate-based approach to both the triangle-finding problem and its NP-hard k-clique generalization. We examine both constant factors for near-term implementation on a Noisy Intermediate Scale Quantum computer (NISQ) device, and the scaling of the problem to evaluate long-term use of quantum computers. We compare the time complexity and circuit practicality of the theoretical approach and actual implementation. We propose and apply two different strategies to the k-clique problem, examining the circuit size of Qiskit implementations. We analyze our implementations by simulating triangle finding with various error models, observing the effect on damping the amplitude of the correct answer, and compare to execution on six real IBMQ machines. Finally, we estimate the date when the methods proposed can run effectively on an actual device based on IBM's quantum volume exponential growth forecast and the results of our error analysis.

An Innovative Near-Field Communication Security Based on the Chaos Generated by Memristive Circuits Adopted as Symmetrical Key

The new technology solutions are playing an important role in the hardware security. One of the latest techniques is the use of the Memristor as an encryption element. In this paper, it has been introduced a two-column array inductor for Memristor-Based Wireless Power Transfer (M-WPT) systems. The traditional WPT circuits are based on switches, which do require a control circuit for timing and have low data encryption factor. By adopting the memristive Chua`s circuit with the chaotic behaviour characteristic, it is possible to create a symmetrical dual-key cryptography. Furthermore, in this innovative solution, the high inductance value of the traditional Chua circuit can be further reduced by using the dynamic effects of the coils flux linkage. The simulation results exhibit the dual-scroll attractors phase portrait, which is available for encryption features. Therefore, the data collected from the phase portrait are used as true random number generator in Python code. Instead of using algorithms, the code can create a symmetrical key for an unique chaotic cryptography. In order to build a prototype, it has been created a PCB design for the whole system. The experiment highlights the unpredictable voltage and current and validates the chaotic behaviour of the transmitter and receiver.

Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS

Energy-efficient timer circuits are required in numerous applications for periodic operations, such as performing measurements and communicating data. In this paper, we present a gate-leakage-based timer that utilizes an amplifier-less replica-bias switching technique to generate a stable frequency, which can operate at a low supply voltage. To guarantee a stable oscillation frequency in a small circuit area, the proposed design adopts an architecture that discharges a pre-charged capacitor through a resistive element (gate-leaking MOS capacitor) with a low-leakage switch. In the proposed switching technique, the low-voltage timer operates by tracking the discharging terminal of the capacitor and biasing the reference voltage of the switch unit, thereby enabling the minimization of the leakage current without the need for analog amplifier circuits. The high supply sensitivity of the timer is addressed by regulating the supply voltage using a native NMOS header (NNH). The proposed design is fabricated using the 55-nm deeply depleted channel (DDC) CMOS technology, which has a strong body coefficient and occupies an active circuit area of 0.0022 mm2. The measurements show that the proposed design can achieve an energy-per-cycle value of 25 pJ/cycle at a supply voltage of 350 mV when body biasing is applied. The measured Allan deviation floor is 200 ppm at room temperature. The timer exhibits an average temperature sensitivity of 810 ppm/°C for four samples. Moreover, a reduction in the supply sensitivity by a factor of 26 using the NNH is demonstrated in an active circuit area of 0.0034 mm2.

Time Stability of Untethered Electronic Switched MIMO Millimeter-Wave Channel Sounders

Untethered channel sounders are used to measure mobile radio propagation channels. As high data rate, millimeter-wave and multiple-input multiple output (MIMO) are considered in the next generation communications systems, knowledge of the propagation channel needs to be studied in high accuracy. Measuring time stability of the clocks in both transmitter and receiver is essential when characterizing relative delay between multipath components (MPCs), absolute delay, angle of arrival (AoA) and angle of departure (AoD) of MPCs. This paper describes timing circuit design of untethered electronic switched MIMO millimeter-wave channel sounders, proposes practical method to remove a constant initial time error, and experimentally estimates time stability of the channel sounders. Time stability is classified in three categories: short-term (in order of microseconds) that impacts relative delay, AoA and AoD; medium-term (in order of minutes) that impacts absolute delay; and long-term stability (in order of days) that can be calibrated. This is the first time to apply standard parameters for measuring clock stability, such as timing Allan deviation (TDEV) and time interval error (TIE), to channel sounding and modeling. Novel methods are developed for measuring jitter and short-term noise. It was found that TDEV for short-term measurements was less than 1 ps and the medium-term timing errors due to clock noise could be maintained at 0.4 ns/min.

Regenerative Braking in Electric Vehicles

This paper deals with the implementation of regenerative braking in electric vehicles using PMDC motor. Regenerative braking is the transformation of the vehicle’s energy when the brakes are applied into a stored energy in the battery, which can be used for some other applications within the vehicle. Short range distance covering characteristics of EVs has always beem a major setback for electric cars gaining popularity among users. The exclusive property of a hybrid electric vehicle to recover the energy lost in the form of heat when the driver applies brakes is a major advantage of a hybrid electric cars and has an edge over the other electric vehicles in the market. This problem is solved by increasing the range of these cars. The majority of the kinetic energy kept in a moving vehicle is wasted as heat and some part of it is absorbed by rolling resistance, mechanical friction and aerodynamics of the vehicle. The present day development to merge the drivetrain and brake systems to provide better traction and stability control can be made simpler with the use of electric drive operation. In this process we use simulation tools like simulink and solid works before going for real time circuit. Aim of this project is to create a sustainable future EV which will be a solution to the fuel crisis in near future

Fredkin Gates Based Testable Reversible Shift Registers

in this paper, we recommend the connection of testable skip registers counting on conformist purpose passages. The proposed detour registers trouble to coordinate protection gateways can play out the flow registers located out in antique fashion entries to the quantity testability. Any reduction lower once more to convey down some unique time circuit situation to those slight method of thinking doors is probably preferred for normal unidirectional stuck-at deficiencies making use of awesome take a look at vectors. those are all of the 1s, and all of the 0s. The systems of vectors testable skip registers are common. The significance of the proposed sketches exists within the way that it offers the relationship of reversible genuinely testable circle registers for any clung in charge via manner of techniques for method for mind boggling test vectors, there with the useful asset of getting out the critical for an series course get valid of get segment to inner reminiscence cells. The execution of ace slave turn-tumbles and twofold detail started out turn-bungles moreover characterised within the paper.

Efficient Classical Simulation of Clifford Circuits with Nonstabilizer Input States.

We investigate the problem of evaluating the output probabilities of Clifford circuits with nonstabilizer product input states. First, we consider the case when the input state is mixed, and give an efficient classical algorithm to approximate the output probabilities, with respect to the l_{1} norm, of a large fraction of Clifford circuits. The running time of our algorithm decreases as the inputs become more mixed. Second, we consider the case when the input state is a pure nonstabilizer product state, and show that a similar efficient algorithm exists to approximate the output probabilities, when a suitable restriction is placed on the number of qubits measured. This restriction depends on a magic monotone that we call the Pauli rank. We apply our results to give an efficient output probability approximation algorithm for some restricted quantum computation models, such as Clifford circuits with solely magic state inputs, Pauli-based computation, and instantaneous quantum polynomial time circuits. Finally, we discuss the relationship between Pauli rank and stabilizer rank.

Timing Circuit Design Based on Sequential Logic and Micro-processing Technology

According to the need of equipment testing, the paper presented the overall scheme of timing circuit and the wiring diagram of hardware circuit, and also designed the indicator circuit, the timing software and the band switch circuit. Then modular design concept and function decomposition method were adopted, and the time sequence step-by-step technology and safety isolation technology were used to solve the difficulty and credibility of acquiring multi-functional components, multi-system modules and complex multi-channel correlated signal interference problem. Finally, the off-line debugging was carried out. The results show that the technology can test the functions and performance indexes of the plug-in board comprehensively and completely, realize the functions of depth setting system debugging, extension testing and fault precise location, and shorten the maintenance and detection time.

Design of Simulated Circuits for the Releasing Device Tester

Aiming at the function test of the releasing device, the encoding circuit was designed by using circuit simulation method, and the full function test of the device was realized by generating analog signals. The timing circuit, power control circuit and band switch circuit were designed by using sequential logic and micro processing technology, and the portable test device for the placement device was designed and implemented. The test results show that the performance of the tester is stable, the test items are complete, and the indicators meet the design requirements.