Circuit Specifications Research Articles

Optimization of Filter and Operational Amplifier Based on Evolutionary Strategy

Optimization of analog circuits relies on engineers’ experience and intuition to find suitable parameters to satisfy circuit specifications. This job is highly labor-intensive, highly repetitive, and time-consuming, but the optimized circuit is sub-optimal. In this paper, the evolutionary strategy is proposed to optimize analog circuit design strategy. The filter designed by engineers and operational amplifier with random generated instances’ parameters are included, and the S parameters of the filter and the gain and dynamic power consumption of the operational amplifier are optimized respectively. The simulation results show that the filter and operational amplifier can be further optimized by using the evolutionary strategy. This method can greatly reduce the workload of analog circuit designers, improve the performance of analog circuits and shorten the design cycle.

Automated Generation of Quantum Circuit Specifications Based on Reed — Muller Expressions

Automated Generation of Quantum Circuit Specifications Based on Reed — Muller Expressions

Revisiting Filtration Fraction as an Index of the Risk of Hemofilter Clotting in Continuous Venovenous Hemofiltration.

Hemofilter clotting is a major challenge in continuous venovenous hemofiltration (CVVH). Experts recommend keeping filtration fraction, the fraction of plasma water that is removed by ultrafiltration, below 20% or 30% to avoid clotting ([1][1]). Clotting risk is believed to markedly increase when

A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

Realization of a design-less system for analog integrated circuits

The 21st century has given rise to a digital world which has significantly impacted on the ways in which humans go about their everyday lives. From being able to speak with whomever you want, whenever you want, wherever you are on your smartphone, to tapping away on your laptop, through to spending hours each day on the internet, the world we live in is firmly digital and it now shapes the way we experience life. When it comes to circuits, analog still has a hugely important role to play. Circuit designer Associate Professor Nobukazu Takai is leading a team of researchers who are applying machine learning to analog circuit design. They are the first team to do this anywhere in the world and, using their method, computers are able to learn how to improve their own circuit specifications.

Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links

The choice of clock and data recovery (CDR) architecture in serial links dictates many of the blocklevel circuit specifications (specs). Block-level specs ultimately determine the energy efficiency of the system. Therefore, to design energy-efficient serial links, it is important to understand the basics of CDR operation, CDR's main performance metrics, and the relationship between circuit-level parameters and system-level performance metrics.

Logic Synthesis of Approximate Circuits

The ability of several important application domains to tolerate inexactness or approximations in a large fraction of their computations has lead to the advent of approximate computing , a new design paradigm that exploits the intrinsic error-resilient nature to optimize computing platforms for energy and performance. A promising approach to approximate computing is to design approximate circuits, or circuit implementations that are highly efficient but differ in functionality from their original specifications subject to a prespecified quality constraint. While a slew of manual design techniques for approximate circuits have demonstrated their significant potential, a key requirement for their mainstream adoption is to develop automatic methodologies and tools that are general and scalable to any given circuit and quality specification. In this article, we propose SALSA, a systematic methodology for automatic logic synthesis of approximate circuits. Given a golden RTL specification of a circuit and a quality constraint that defines the amount of error that may be introduced in the implementation, SALSA synthesizes an approximate version of the circuit that adheres to the prespecified quality bounds. We make two key contributions: 1) the rigorous formulation of the problem of approximate logic synthesis (ALS), enabling the generation of circuits that is corrected by construction and 2) mapping the problem of approximate synthesis into an equivalent traditional logic synthesis problem, thereby allowing the capabilities of existing synthesis tools to be fully utilized for ALS. In order to achieve these benefits, SALSA forms a virtual quality constraint circuit (QCC) that encodes the quality constraints using logic functions called Q-functions . It then captures the flexibility that engendered by them as approximation don’t cares (ADCs), which are used for circuit simplification using traditional don’t care-based optimization techniques. We utilized SALSA to automatically synthesize approximate circuits ranging from arithmetic building blocks (adders, multipliers, and MAC) to entire datapaths (DCT, FIR, IIR, SAD, FFT Butterfly, and Euclidean distance), demonstrating scalability and significant improvements in area ( $1.1\times $ to $1.85\times $ for tight error constraints, and $1.2\times $ to $4.75\times $ for relaxed error constraints) and power ( $1.15\times $ to $1.75\times $ for tight error constraints, and $1.3\times $ to $5.25\times $ for relaxed error constraints).

60-GHz Low-Noise VGA and Interpolation-Based Gain Cell in a 40-nm CMOS Technology

This paper presents the design and measurement of an interpolation-based low noise and variable gain cell (IBA-cell) in the 60-GHz band, using a 40-nm CMOS technology. The interpolation-based gain cell is designed for an innovative analog beamforming front end, where the array pattern is not only controlled in the phase domain, but also wins the flexibility in the magnitude domain. The circuit specifications are first derived for the application at 60 GHz. Techniques to combine low noise figure (NF) with variable gain tuning are presented focusing on the NF and linearity (IIP3) on the example of a 60-GHz low noise amplifier and variable gain amplifier. Subsequently, the design and measurement of the whole gain cell (IBA-cell) integrated into a single chip are reported with the technique of a cross-coupled feedback loop to reduce the phase variations over the gain tuning states and enhance the variations of IIP3. The IBA-cell achieves 15.8-dB maximum gain and 6.5-dB NF at 57 GHz with the gain tuning range from −2 to 15.8 dB and IIP3 varying from −11.3 to −16 dBm over the gain control range. The IBA-cell consumes a dc power of maximum 54 mA from 1.1 V.

Model Reduction for Optimized Online Compensation of Hysteresis and Creep in Piezoelectric Actuators

In this brief, a strategy is proposed for the identification, starting from experimental measurements on piezoelectric actuators, of all the parameters of the recently proposed power-law hysteresis and creep model. The algorithm allows trading off modeling accuracy and speed of the inverse model (compensator) implemented in a digital device. An analysis of the relationships among parameters and their effects on modeling and circuit performances is also carried out. The proposed strategy is tested on two piezoelectric actuators, showing that the obtained models are able to fulfill the circuit specifications.

Nonlinear Energy Harvesting for Millimeter Wave Networks With Large-Scale Antennas

In this paper, an analytical framework is proposed to explore the potential of wireless power transfer (WPT) for a millimeter wave (mmWave) network with large-scale antennas. Prior works mostly focus on WPT systems with a linear energy harvesting (EH) model, which cannot properly capture the power dependent EH efficiency. On the other hand, based on a nonlinear EH model, the effect of practical EH circuit specifications on the EH performance can be analyzed. By using stochastic geometry approach, analytical and asymptotic expressions for the energy coverage probability, average harvested energy, and achievable rate are derived under different base station (BS) configuration and deployment scenarios. Numerical results provide interesting design insights that the EH circuit specifications significantly affect the network performance. Increasing the BS density and number of BS antennas can improve the network performance. Due to saturation of EH circuits, the typical receiver can only achieve finite maximum amount of harvested energy and achievable rate even when the BS has a large number of antennas.

DESIGN OF SECOND ORDER BUTTERWORTH HIGHPASS FILTER USING CMOS TECHNOLOGY

The research Complementary Metal-Oxide Semiconductor (CMOS) Technology for Design of second order butterworth highpass filter IC. This is caused CMOS have excellence low power dissipation and small size. This research aims to know performance, quality and reliability second order butterworth highpass filter circuit. The method used to problem solving, analysis with the literature and the simulation use pspice program for exam the specification of circuit. To make IC picture using DSCH software and layout circuit using Microwind program. From examination result -2,99dB for gain voltage parameter, frequency -40dB and 88,25° phase shift second order highpass filter. The result of this circuit have low power dissipation although applied to second order highpass filter equal 2,28mW better than generality IC second order highpass filter (GH580). Wide of layout circuit is 1110µm x 385µm DOI : https://doi.org/10.26905/jeemecs.v1i1.2299

Design of Battery Charging Control System (Fast Charging) on Electric Vehicle based on Atmega32 Microcontroller

Electric Vehicles are vehicles that do not release toxic gases that can reduce environmental pollution caused by combustion. The electric vehicle requires a lithium ion battery as a replacement energy source of fuel oil so it needs charging a battery that can speed up charging safely. This research uses fast charging method through high current method and adjusts the current capacity needed by the battery in accordance with the result of circuit specification. This research uses rectifier circuit, buck converter, Atmega microcontroller. The results of this study are expected to increase current capacity and speed up the process of charging the battery.

Single event transients mitigation techniques for CMOS integrated VCOs

Single event transients (SETs) in analog integrated circuits result from the interaction of a heavy ion or high-energy proton with a sensitive p-n junction. SETs induce electron-hole pairs that can lead to current spikes, which propagate through the integrated circuit and can result in substantial transient peaks at the output voltage. This paper proposes techniques to mitigate SETs in CMOS voltage controlled oscillators (VCOs) without affecting circuit specifications. A VCO was designed to meet the IEEE 802.15.4 specifications. First, the weakest nodes were detected, and then particle strikes with a LET ranging from 14.47 to 57.86 MeV cm2 mg−1 were applied at these nodes. Amplitude variation, recovery time and phase shift were obtained at the output nodes. RHBD techniques are discussed and applied to redesign the VCO. The proposed mitigation techniques reduce the recovery time by approximately 59%, the output phase displacement by 74.2% and the amplitude variation by 96.7%.

High downforce race car vertical dynamics: aerodynamic index

ABSTRACTRace car performance is strongly affected by aerodynamics. Due to downforce generated by the vehicle floor (i.e. diffuser), vehicle ride heights are key parameters to improve performance, and the coupling of aerodynamics and suspension is one of the key points of race car setting. This work focuses on the suspension and aerodynamic coupling from the vertical dynamics point of view. Besides road holding performance, for race cars, aerodynamic performance and stability are major factors. Downforce decreases laptime (the main performance target) but pitch instability is a non-desired effect that can happen in high downforce race cars. A new vertical dynamic performance index is proposed through the use of simulation to improve aerodynamic performance and understand the pitch instability phenomenon. This new index uses all relevant vehicle nonlinearities related to vertical dynamics and can handle a specific track profile and vehicle speed range, allowing the analysis be conducted according to a circuit specification. A previously validated Formula 3 car model was used as an example.

Analog Circuit Specification Testing by Means of Walsh\u2013Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

This paper describes an approach for an analog electronic circuit specification quick verification that is based on a simple mathematical model determined during the before-test stage statistical analysis. Generally, the observed performance parameters (e.g., cutoff frequency, phase shift at the assumed frequency point) are calculated from the Walsh–Hadamard transform components of circuit under test step time response. The optimal estimating formulas for relationship between the tested specifications and the selected components of the spectra are defined in the system based on a linear multiple regression procedure supported by genetic programming. The evolutionary computations significantly improve the approximation effectiveness by selecting the most representative points of the sequences domain and by defining the optimal set of linearizing functions. Finally, at the test stage, only a simple step stimulus and time-effective calculations are required to the tested performance parameters (specifications) of analog circuit identification and it predisposes the approach to quick production testing procedure realization or to embedding it in the mixed-signal systems. The automated built-in self-testing procedure using this concept may be easily implemented to low-cost microcontroller equipped with AD converter used for the testing response samples acquiring.

Rate-Energy Region of SWIPT for MIMO Broadcasting Under Nonlinear Energy Harvesting Model

This paper explores the rate-energy (R-E) region of simultaneous wireless information and power transfer for MIMO broadcasting channel under the nonlinear radio frequency energy harvesting (EH) model. The goal is to characterize the tradeoff between the maximal energy transfer versus information rate. The separated EH and information decoding (ID) receivers and the co-located EH and ID receivers scenarios are considered. For the co-located receivers scenario, both time switching (TS) and power splitting (PS) receiver architectures are investigated. Optimization problems are formulated to derive the boundaries of the R-E region s for the considered systems. As the problems are nonconvex, we first transform them into equivalent ones and derive some semi-closed-form solutions, and then design efficient algorithms to solve them. Numerical results are provided to show the R-E region s of the systems, which provide some interesting insights. It is shown that all practical circuit specifications greatly affect the system R-E region. Compared with the systems under traditional linear EH model, the ones under the nonlinear EH model achieve smaller R-E region s due to the limitations of practical circuit features and also show very different R-E tradeoff behaviors.

Closed Grinding Circuit Design of Cu-Ni-Co-Fe-S Matte

Bond work index of Cu-Ni-Co-Fe-S matte having different sulfur contents was measured, followed by closed grinding circuit design which consisted of ball mill and spiral classifier. At first, the mineralogical and chemical contents of the matte was analyzed using XRF and SEM-EDS method. Afterward, Grinding work index of matte was estimated using the Bond work index test. The work index measured was used to determine grinding circuit specification lastly. It was found that the more the sulfur concentration was in the matte, the less Bond work index value was as sulfur contents increased from S 15.9 wt.% - S 24.9 wt.%. As a result, the grinding energy was reduced up to 45% in the range. For grinding process design, Closed grinding circuit was compared with open grinding circuit, in which hydrocyclone and spiral classifier were also investigated.

A Study on the FPGA Implementation of the Bilateral Control Algorithm Towards Haptic Teleoperation

This paper presents the FPGA implementation of the sliding mode control algorithm for bilateral teleoperation, such that, the problem of haptic teleoperation is addressed. The presented study improves haptic fidelity by the widening the control bandwidth. For wide control bandwidth, short control periods as well as short sampling periods are required that can be achieved by FPGA. The presented FPGA design methodology applies basic optimization methods in order to meet the requirements in terms of the control period and the hardware resource consumption. The circuit specification was performed by the high-level programing language LabVIEW and using the fixed-point data type. Furthermore, the design methodology allows achieving short design times for producing the FPGA logic circuit. The proposed FPGA-based bilateral teleoperation was validated by 2-DoF master-slave experimental device.

Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes

This paper presents an energy-autonomous wireless communication system for ultra-small Internet-of-Things (IoT) platforms. In the proposed system, all necessary components, including the battery, energy-harvesting solar cells, and the RF antenna, are fully integrated within a millimeter-scale form factor. Designing an energy-optimized wireless communication system for such a miniaturized platform is challenging because of unique system constraints imposed by the ultra-small system dimension. The proposed system targets orders of magnitude improvement in wireless communication energy efficiency through a comprehensive system-level analysis that jointly optimizes various system parameters, such as node dimension, modulation scheme, synchronization protocol, RF/analog/digital circuit specifications, carrier frequency, and a miniaturized 3-D antenna. We propose a new protocol and modulation schemes that are specifically designed for energy-scarce ultra-small IoT nodes. These new schemes exploit abundant signal processing resources on gateway devices to simplify design for energy-scarce ultra-small sensor nodes. The proposed dynamic link adaptation guarantees that the ultra-small IoT node always operates in the most energy efficient mode for a given operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various classes of new applications, such as implanted smart-dust devices.

Superconducting Digital Circuit Design With an Open Source and Freeware Tool Chain

Superconducting digital circuits have been around for decades, but recent projects that exploit such circuits for low-power, high-performance computing are rapidly maturing superconducting circuit technologies. As a result of increasing circuit complexity, there is renewed focus on superconducting digital circuit design tools. Until now, most computer-aided design (CAD) tool development for superconducting electronics (SCE) circuit design has been based on calibrating semiconductor tools, rather than creating new technology-specific tools for the SCE circuit design. The recent development shows bias toward large and expensive CAD tools. These tools, or modules developed for commercial semiconductor CAD tools, require users to have access to an expensive commercial semiconductor CAD software, which places it out of the reach of new entrants or small research groups in SCE. In this paper, the open-source tools that can be used as alternatives to form an SCE design tool chain are described. All the design stages in an SCE integrated circuits design flow, from circuit specification down to layout design, are noted in this paper. Each stage is discussed and the available open-source tools are described. The inherent disadvantages of these open-source tools are also pointed out. A design example is then provided to demonstrate a complete open source and freeware tool chain.