Integrated Circuits Research Articles

Printed Interconnects for Heterogeneous Systems Integration on Flexible Substrates

AbstractHeterogeneous integration on flexible substrates has been explored in recent years to meet the high‐performance and flexible form factors requirements of several emerging applications. Reliable interconnects, in both 2D and 3D layouts, are critical for the effective use of these systems. But it is challenging to employ conventional bonding and interconnect technology due to considerable mismatches in mechanical and thermal properties. For example, the ultra‐thin chips (UTCs) are too fragile to withstand the static or oscillating forces applied during conventional bonding. In this regard, printing of metal tracks on flexible substrates is a promising alternative to access the contact pads on integrated circuits (ICs), as the interconnects on diverse substrates can be realized at room temperature processing using as much materials as needed. Further, it is easier to attain step coverage. Considering the above attractive features, and the challenges associated with conventional bonding techniques, this article focuses on the development of high‐resolution printing interconnects in both 2D and 3D layouts and explores various printing routes available for high density integration. The article also discusses major conventional interposers/interconnects forming methods and their limitations for flexible hybrid electronics along with few examples of printed interconnects to highlight the opportunities for future.

Development of a virtual teaching module for advanced semiconductor fabrication and its learning effectiveness analysis

AbstractSemiconductor fabrication is the process of manufacturing semiconductor devices, typically integrated circuits (ICs) such as microprocessors and memory. This involves transferring circuit diagrams onto a silicon wafer using photomasks and photoresists. After a series of fabrication processes, ICs are created on the wafer surface and then diced into individual chips, which are packaged and tested with quality control procedures to become the final products. Virtual reality (VR) simulates imaginary experiences or environments difficult to achieve in the real world through human senses and immersive equipment, allowing users to interact in a virtual 3D space in real time, making it well suited for applications in science education and industrial training. This study transforms the essential knowledge of advanced semiconductor manufacturing processes into an easily understandable virtual teaching module, thereby creating educational resources for high school and college students. The objective is to enhance their scientific and technological literacy, yielding substantial benefits for the general public. This study utilized VR technology to simplify and clarify the knowledge about the semiconductor manufacturing process, making it more engaging for learners. The virtual teaching module's learning content includes an overview of wafer preparation, semiconductor fabrication, chip packaging, and IC testing. Users can interact with the virtual teaching module and conduct virtual experiments to enhance their understanding by trial and error. Experimental results show that it can improve students' learning achievement and learning motivation. Therefore, the virtual teaching module is suitable for high‐school students and the general public to understand semiconductor technology and its applications. The effectiveness of the virtual teaching module is heavily dependent on the availability and quality of VR hardware and software. Limited access to advanced VR equipment or technical issues could have affected the learning experience, thereby influencing the learning outcomes.

Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. This step is known as circuit partitioning. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc, are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA), Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption for addressing the VLSI circuit partitioning problem. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO, 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system’s average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA based methods also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

100-nm Broadband and Ultra-compact Multi-dimensional Multiplexed Photonic Integrated Circuit for High-capacity Optical Interconnects

100-nm Broadband and Ultra-compact Multi-dimensional Multiplexed Photonic Integrated Circuit for High-capacity Optical Interconnects

Radiation Hardened Read-Stability and Speed Enhanced SRAM for Space Applications

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications.

Terminal differentiation precedes functional circuit integration in the peduncle neurons in regenerating Hydra vulgaris

Understanding how neural circuits are regenerated following injury is a fundamental question in neuroscience. Hydra is a powerful model for studying this process because it has a simple neural circuit structure, significant and reproducible regenerative abilities, and established methods for creating transgenics with cell-type-specific expression. While Hydra is a long-standing model for regeneration and development, little is known about how neural activity and behavior is restored following significant injury. In this study, we ask if regenerating neurons terminally differentiate prior to reforming functional neural circuits, or if neural circuits regenerate first and then guide the constituent naive cells toward their terminal fate. To address this question, we developed a dual-expression transgenic Hydra line that expresses a cell-type-specific red fluorescent protein (tdTomato) in ec5 peduncle neurons, and a calcium indicator (GCaMP7s) in all neurons. With this transgenic line, we can simultaneously record neural activity and track the reappearance of the terminally-differentiated ec5 neurons. Using SCAPE (Swept Confocally Aligned Planar Excitation) microscopy, we monitored both calcium activity and expression of tdTomato-positive neurons in 3D with single-cell resolution during regeneration of Hydra’s aboral end. The synchronized neural activity associated with a regenerated neural circuit was observed approximately 4 to 8 hours after expression of tdTomato in ec5 neurons. These data suggest that regenerating ec5 neurons undergo terminal differentiation prior to re-establishing their functional role in the nervous system. The combination of dynamic imaging of neural activity and gene expression during regeneration make Hydra a powerful model system for understanding the key molecular and functional processes involved in neural regeneration following injury.

The impact of big fund on the operational efficiency of semiconductor companies: Corporate social responsibility as a non-economic output

This study contributes to research on the total factor operational efficiency of the semiconductor company considering corporate social responsibility (CSR) by proposing a novel integer-valued nonparametric frontier method. This method adopts an endogenous directional distance function, which first selects the benchmark and then endogenously determines the directional vector. Avoiding the issue of non-integer slack adjustment increases the convenience of formulating incentive plans and calculating efficiency. We apply this method to the input–output data of 185 listed Chinese semiconductor companies from 2010 to 2022, considering integer-valued CSR as non-economic output. Global Malmquist productivity index analysis shows that the average total factor operational efficiency of companies that received investment from the National Integrated Circuit Industry Investment Fund (Big Fund) increased by 6.9%. Using the econometric technique, we verify that the total factor operational efficiency of semiconductor companies receiving Big Fund investment increased by 0.084 compared to those without Big Fund investment. Heterogeneity analysis showed that the effect of Big Fund was more significant in improving the total factor operational efficiency of state-owned, new, and non-integrated circuit semiconductor companies, implying the necessity of purposeful investment policies for the Big Fund.

Scaling of N-Type Field-Effect Transistors Based on Aligned Carbon Nanotube Arrays.

Wafer-scale aligned carbon nanotubes (A-CNTs) are promising candidate semiconductors for building high-performance complementary metal-oxide-semiconductor (CMOS) transistors for future integrated circuits (ICs). A-CNT-based p-type field-effect transistors (P-FETs) have demonstrated excellent performance and scalability down to sub-10 nm nodes. However, the development of A-CNT n-type FETs (N-FETs) lags far behind, in regard to their electronic performance and device scaling. In this work, we fabricated top-gated N-FETs based on A-CNTs with a scandium (Sc)-contacted source and drain. High-performance A-CNT N-FETs were demonstrated with record on-state current (Ion) exceeding 1 mA/μm and peak transconductance (gm) of 0.4 mS/μm. Interestingly, the A-CNT N-FETs exhibited abnormal scaling behavior owing to the lateral oxidation of low-work function source/drain contacts, leading to formidable challenges to scale both the gate length (Lg) and the contact length (Lc) at the same time. Understanding of the abnormal scaling behavior contributes to seeking solutions for high-performance A-CNT N-FETs, and it paves the way for future CNT CMOS digital IC technology.

High-voltage thermocell modules for direct device operation: eliminating the need for DC-DC converters

Abstract This study explores the potential of thermocells as an efficient energy-harvesting solution that can power practical devices without the need for a DC-DC converter. We constructed thermocell devices comprising 35 legs using a modified soldering technique and electrode treatment to improve reliability. The devices achieved a peak voltage of 3.5 V at a hot-side temperature of 60 °C under natural cooling conditions. These thermocells were integrated with a voltage detector integrated circuit (IC) and beacon, initiating beacon operation within 100 s and transmitting signals over 600 times within a 15 min period. Our findings demonstrate the feasibility of thermocells as an alternative energy source, offering a cost-effective and streamlined approach for energy-harvesting applications without the complexity and expense of DC-DC converters.

Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies

As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin’s surface roughness and results in a high interfacial state density (D it ), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel D it by 73.31% vs 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV dec−1, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Flexible modular strategy for tailored, human–machine fusion wearable electronics

Over the past three decades, the field of wearable electronics has experienced significant growth, with future developments expected to lead to more seamless integration and a profound symbiosis between humans and electronic systems. However, current developments in wearable technology are constrained by traditional integrated circuit (IC) design paradigms and a limited range of form factors, predominantly manifesting as watches, glasses, and rings with fixed functionalities and performance capabilities. This study proposes a modular design method that leverages flexible electronics for tailoring wearable devices according to specific needs. This approach disperses and reinterprets the integrated device forms through the guidance of human body morphology and conformal design principles. The functional units within these wearable devices are constructed as physically isolated, flexible modules within a robust bus structure. These modules can be easily integrated using magnetic attachments and connectors, which allows for the creation of unconventional wearable devices with customised functionalities and forms. To validate this approach, a series of flexible functional modules were designed and prototyped. Demonstrations of some of these integrated wearable forms, including watches, headbands, and gloves, highlight the versatility of this approach. These devices can be rapidly assembled with selected flexible modules capable of monitoring vital signs, such as heart rate, peripheral capillary oxygen saturation (SpO2), barometric pressure, humidity, and temperature. The results suggest that the proposed modular method holds significant potential for advancing the development of future human–machine fusion wearable electronics.

Flexible electronic-photonic 3D integration from ultrathin polymer chiplets

Integrating flexible electronics and photonics can create revolutionary technologies, but combining these components on a single polymer device has been difficult, particularly for high-volume manufacturing. Here, we present a robust chiplet-level heterogeneous integration of polymer-based circuits (CHIP), where ultrathin polymer electronic and optoelectronic chiplets are vertically bonded at room temperature and shaped into application-specific forms with monolithic Input/Output (I/O). This process was used to develop a flexible 3D integrated optrode with high-density microelectrodes for electrical recording, micro light-emitting diodes (μLEDs) for optogenetic stimulation, temperature sensors for bio-safe operations, and shielding designs to prevent optoelectronic artifacts. CHIP enables simple, high-yield, and scalable 3D integration, double-sided area utilization, and miniaturization of connection I/O. Systematic characterization demonstrated the scheme’s success and also identified frequency-dependent origins of optoelectronic artifacts. We envision CHIP being applied to numerous polymer-based devices for a wide range of applications.

Optimization of cooling process under varied pulsed conditions in multi-stage thermoelectric systems

This paper addresses the issue of thermoelectric cooling in a pulsed quasi-steady state (repetitive) condition. This situation occurs, for example, for an electronic integrated circuit performing demanding tasks in a discontinuous manner. Using heat reservoirs of selected capacity that are part of the thermoelectric system and appropriate shaping of the time profile of the supplied electrical current, cooling temperatures not achievable in the steady state for the system can be reached in a pulsed manner for a specified period. This process is subject to optimisation. The analysis was carried out for a two-stage system with an internal (interstage) heat reservoir of a given thermal capacity. The aim of the study was to find the relationship between the level of the supercooling temperature, its repeatability and the ability to maintain this temperature for a given time. To this end, two supply current waveforms were adopted and optimised both without and with contact thermal resistance in the system. The lowest subcooling temperature of about 7 K lower than the steady-state temperature was obtained for a very long period and a very short holding time. Decreasing the period or increasing the holding time results in a non-linear increase in temperature. Similar effects are obtained for the contact thermal resistance present in each layer. A full map of the period-thermal resistance–temperature relationship was determined, as well as the supercooling potential curves.

Integrated thermo-optic phase shifters for laser-written photonic circuits operating at cryogenic temperatures

Abstract Integrated photonics offers compact and stable manipulation of optical signals in miniaturized chips, with the possibility of changing dynamically their functionality by means of integrated phase shifters. Cryogenic operation of these devices is becoming essential for advancing photonic quantum technologies, accommodating components like quantum light sources, single photon detectors and quantum memories operating at liquid helium temperatures. In this work, we report on a programmable glass photonic integrated circuit (PIC) fabricated through femtosecond laser waveguide writing (FLW) and controlled by thermo-optic phase shifters both in a room-temperature and in a cryogenic setting. By taking advantage of a femtosecond laser microstructuring process, we achieved reliable PIC operation with minimal power consumption and confined temperature gradients in both conditions. This advancement marks the first cryogenically-compatible programmable FLW PIC, paving the way for fully integrated quantum architectures realized on a laser-written photonic chip.

First-principal analysis and design of TaPO5-based waveguides for photonic circuitry

With the rapid development of telecommunication systems, supercomputers, and large data centers, there is a growing need for advanced photonic materials to overcome the limitations of traditional photonic circuitry. This paper introduces monoclinic TaPO5, an indirect-bandgap semiconductor material, as a compact platform for photonic integrated circuits. TaPO5, with a bandgap of 2.148 eV, is analyzed for its structural, vibrational, thermodynamic, and optical properties using pseudo-potential plane waves within the density functional theory (DFT) framework. Our analysis reveals that TaPO5's thermodynamic properties, such as entropy, internal energy, and heat capacity, increase with temperature, while Helmholtz's free energy decreases. The materials demonstrate favorable optical characteristics, including a refractive index (n) of 2.11, an extinction coefficient (k) of 1.2 × 10⁻⁵, and a dielectric function with a real part of 4.45 and an imaginary part of 5.1 × 10⁻⁵ at a wavelength of 1.55 μm. TaPO5 exhibits promising performance metrics for photonic applications. Specifically, a proposed 1 × 2 multimode interference (MMI) splitter demonstrates 0.03 dB excess loss, a compact footprint of 4 × 18 μm2, and a 50:50 splitting ratio at 1.55 μm. These findings indicate that TaPO5 is a viable material for next-generation photonic integrated circuits, offering theoretical and practical advantages for various applications in photonic technology.

Structural designs and synthesis of co-polycarbonates with cyclohexyl and fluorene structures: Low-dielectric constant, high solubility, and superior mechanical properties

The rapid developments of high-speed communication and large-scale integrated circuits have accelerated the research for insulating dielectric materials with low dielectric constant, low dielectric loss, and good mechanical properties. In this study, a series of polycarbonate resins containing cyclohexyl and fluorene structures are synthesized by melt transesterification, which is low dielectric, highly thermally resistant, and soluble. The effects of fluorene structure contents on the properties of a co-polycarbonate resin were studied systematically. The results showed that the non-polar fluorene group could reduce the molecular polarization of co-polycarbonate, resulting in low permittivity of co-polycarbonate are 2.41-2.71@1MHz. In addition, the resin has excellent solubility and can be dissolved in NMP, CH2Cl2, THF, and other solvents at room temperature. Furthermore, the co-polycarbonate resins also exhibit superior heat resistance with glass transition temperature (Tg) of 160.6-173.1 °C as well as admirable mechanical properties with a tensile strength of 50.54-70.72 MPa. This makes it a promising candidate for high-speed communications and large-scale integrated circuits.

PHOTONIC INTEGRATED CIRCUITS: GIANT LEAP IN COMPUTING TECHNOLOGY

There is a continued demand for increase in computing requirements from sensor, smartphones, to servers. However, the technology improvements in clock speed, power, and memory bandwidth from traditional electronic integrated circuits (EIC) has started to saturate. This has triggered further research in exploration of photon integrated circuits (PIC) that utilize photons (or particles of light) as opposed to electrons to form a functioning circuit. Research suggests that by integrating the benefits of EIC and PIC, one is able to harness the best of both worlds. The inherent advantages of photonics technology such as speed, energy-efficiency, and density, coupled with the advances in material technology, make them suitable to address the challenge of designing heterogeneous chips. This paper presents the fundamentals of the photonic technology, applicability to solving digital computing problems, ability to integrate into PICs, and its capability to complement electronic integrated circuits for powering the computing demands of emerging applications.

The Embedded System of Battery Charging with Constant Current System using Microcontroller and IC LM338

The battery has the function of an electrical energy storage system. However, charging the battery is prone to damage. Damage to the battery is often caused by overcharging. The time used during the battery charging process is an important factor that must be considered when charging. thus, efficient battery charging is important and very necessary to avoid damage. An another important aspect of a battery charging method is the current and voltage values supplied during its charging process. The presence of inappropriate values damages and reduce battery life, while the maintenance of a constant current is an important charging process step that extends service life. This research is expected to create a safe and optimal battery charging system with a simple low-cost circuit based on constant current by utilizing the LM388 Integrated Circuit (IC) regulator. This study discusses a 12 V battery charging system with monitored and controlled constant current using an R-Shunt sensor. Voltage monitoring while charging was carried out with voltage sensors using a constant current of 0.1 to 1.3 Ampere. Furthermore, voltages and currents were displayed through a Liquid Crystal Display (LCD) screen controlled with Arduino Uno during battery charging. The measurement results showed that the circuit reached voltages and currents of 14.07 V and 0.19 A respectively for a charge duration of 8 hours.

Layout Congestion Prediction Based on Regression-ViT

To accelerate the back-end design flow of integrated circuit (IC), numerous studies have made exploratory advancements in machine learning (ML) for electronic design automation (EDA). However, most research works are limited to deep learning (DL) models predominantly based on convolutional neural networks, and the models often suffer from poor generalization due to the scarcity of data. In this study, we propose the Double generative adversarial networks (D-GAN) model to enrich the dataset and propose the Regression Vision Transformer (R-ViT) model to predict layout congestion information. Compared to the baseline model, experimental results show improvements of 3.03% and 2.64% in Receiver Operating Characteristic-Area under Curve (ROC-AUC) and Precision-Recall Curve-Area under Curve (PRC-AUC) respectively. To further enhance the prediction accuracy of the model, an adaptive Huber loss function is designed to optimize the training process, resulting in an improvement of up to 11.03% in ROC-AUC compared with the baseline model. Lastly, extended experiments are conducted to study the effects of parameters and convolutional kernel size on performance, which find a better configuration.

A 220 GHz GaN‐based monolithic integrated frequency doubler delivering over 0.25 W output power

AbstractA 220 GHz GaN‐based monolithic integrated frequency doubler with high continuous‐wave output power has been developed. The doubler achieves improved heat dissipation by establishing the terahertz (THz) monolithic integrated circuit topology with GaN Schottky barrier diodes integrated on a high thermal conductivity SiC substrate. It features six anodes to enhance the power‐handling capabilities. A refractory Schottky metal stack is adopted for better thermal stability. The doubler realizes satisfactory performance by introducing the suspended microstrip and an all‐in‐one output structure. For verification, a prototype of the proposed frequency doubler was fabricated and tested. Measured results show that the proposed doubler produces a continuous‐wave output power of 255 mW at 220 GHz with an efficiency of 14.6%, exhibiting excellent potential for powerful THz sources.