Circuit Design Optimization Research Articles

Investigation on the I⁻V Kink Effect in Large Signal Modeling of AlGaN/GaN HEMTs.

The effect brought by the I–V kink effect on large signal performance of AlGaN/GaN high electron mobility transistors (HEMTs) was investigated in this paper. An improved compact model was proposed to accurately characterize the I–V kink effect. The bias dependence of the I–V kink effect has also been taken into consideration. AlGaN/GaN HEMTs with different gate width were utilized to validate the proposed model. Built on the proposed model, the effect brought by the I–V kink effect on large signal performance has been studied. Results show that the I–V kink effect will lead to the degradation of characteristics, including output power, gain, and power-added efficiency at the saturation region. Furthermore, the influence of the I–V kink effect was found to be related with the input power and the static bias point in this work. The time domain waveform and AC dynamic load line were used for validation of results based on simulation. The consequences of this paper will be useful for the optimization of practical circuit design.

A Lumped RF Model for Nanoscale Memristive Devices and Nonvolatile Single-Pole Double-Throw Switches

In this paper, a scalable lumped model that accurately predicts the steady-state high-frequency behavior of nanoscale RF memristive devices is presented. The model is described 1) analytically by a set of closed-form equations that determine the parameters based on the device physical structure, allowing for optimized circuit design and performance through structure modifications, and 2) numerically to fit the model parameters to experimental data, allowing for evaluation of the accuracy of the model. This model is, to the best of our knowledge, the first lumped RF memristor model that includes device parasitics obtained from empirical measurements reported in the literature. Results show that the model is reasonably accurate, with 9.6% and 13% relative RMS error for the on-state magnitude and phase, respectively. Furthermore, we propose three topologies (series, shunt, and series-shunt) of nonvolatile single-pole double-throw switches using our lumped RF memristor model. The series and shunt topologies are single-voltage-controlled, while the series-shunt requires two control signals. Simulation results of these topologies exhibit low insertion loss and high isolation (below 0.25 dB and over 63 dB, respectively). The added nonvolatility and nanoscale size will result in reduced power consumption and higher density devices.

IBM POWER9 circuit design and energy optimization for 14-nm technology

Modern multicore microprocessors require attentive development to energy requirements when maximizing power-performance efficiency and ensuring reliable plus scalable functionality. IBM POWER9 relies on extensive modeling to identify representative workloads used when analyzing thermal design power and regulator design power against product requirements. Compounding benefits of circuit optimizations applied to the diverse subcomponents of the chip results in lower power cores, caches, and memory/IO interconnect. Specific dc- and ac-current analyses ensure proper definition of chip specifications for system voltage and current delivery. Finally, a systematic exploration of microbenchmarks on intermediate and final POWER9 hardware provides insight into processor core requirements while validating model accuracy.

A Scalable Multiharmonic Surface-Potential Model of AlGaN/GaN HEMTs

An accurate physical model for GaN high-electron-mobility-transistors (HEMTs) device is imperative and crucial for circuit design and technology optimization. In this paper, a scalable large-signal surface-potential (SP) model of AlGaN/GaN HEMTs is presented. The drain current model is capable of accurately modeling the self-heating effect and trapping effect. The self-heating effect is modeled by embedding temperature increment into free-carrier mobility model, and the trapping effect is modeled by introducing an indirect variable effective gate voltage $V_{\mathrm {gseff}}$ . Moreover, the scaling and multiharmonic characteristics of the SP model are studied for the first time. The geometry-dependent thermal resistance $R_{\mathrm {ths}}$ is identified by the electrothermal finite-element method simulations, which is scalable with the gate width W and power dissipations $P_{\mathrm {diss}}$ of the device. Single-tone on-wafer load–pull measurements at operating frequency 8 GHz is carried out for verification purpose. Accurate predictions of the static (dc) $I\!-\!V$ , pulsed-gate-and-drain $I\!-\!V$ , S-parameters up to 40 GHz and large-signal harmonic performance (the fundamental, second- and third-harmonics output power, and power-added efficiency) for the devices with different gate peripheries have been achieved by the proposed model. The results of this paper can pave the way for the full application of the physical-based model in circuits design.

A Radiation-Hardened and ESD-Optimized Wireline Driver With Wide Terminal Common-Mode Voltage Range

In complex environment, the wireline voltage driver should be compatible with wide-terminal common-mode range, electrostatic discharge (ESD), and radiation interference. The most vulnerable devices in the conventional driver are the nMOS transistor and the silicon-controlled rectifier (SCR) against negative the ESD shock, total dose radiation, and single-event latch-up. In this paper, a reliable wireline driver circuit is proposed compatible with −7 ~ 12-V terminal common-mode voltage range. By adopting face-to-face diodes, pMOS/n-p-n hybrid driver, and Schottky diodes, the proposed driver circuit demonstrates significant protection level improvement for both ESD and radiation. Both the reference SCR-based driver and the proposed driver with the optimized circuit design and protection strategy are fabricated using a 0.6- $\mu \text{m}$ bipolar-CMOS-DMOS process. Due to a simpler circuit structure, the proposed output stage has about 10% less chip area. According to the measurement results, the human-body-model ESD level of 3 kV, total dose radiation level of 100 krad(Si), and single-event effect level of 75 MeV $\cdot $ cm2/mg are achieved in the proposed design to satisfy complex environment applications.

A hierarchy in mutation of genetic algorithm and its application to multi-objective analog/RF circuit optimization

This paper presents a multi-objective analog circuit design optimization tool using genetic algorithm based on hierarchical mutation scheme. The idea is to improve the convergence and diversity of genetic algorithm by incorporating hierarchy during polynomial mutation operation. In this regard, a theoretical framework of proposed genetic algorithm is presented using Markov chain principle. To investigate the effectiveness of hierarchy in polynomial mutation operator, the scheme is compared with six different mutation strategies. Experiments are performed for different function evaluations to evaluate the performance of hierarchical polynomial mutation operator. Further, to showcase the improvement in genetic algorithm, numerous experiments are performed on twelve different test functions and two design examples. The proposed genetic algorithm shows competitive performance over other standard optimization techniques in terms of both convergence and diversity of solutions.

Effect of body bias and temperature on low-frequency noise in 40-nm nMOSFETs

This study investigated the effects of temperature and body bias on drain current flicker noise (1/f) in 40-nm nMOSFETs. The 1/f noise is attributable to the charge number fluctuation correlating with the mobility fluctuation. At 300K, as the depletion width was decreased, 1/f noise decreased with the body bias from −0.5 to +0.5V in the weak inversion; conversely, 1/f noise was independent of the body bias because of the neglected depletion charge capacitance in the strong inversion. When the temperature was below 150K, 1/f noise increased when the drain voltage was low because of the Fermi level toward the band edge, which has a higher trap density and corresponds to the inverse square of the subthreshold swing. However, when the drain voltage was high, 1/f noise was dominated by the mobility fluctuation because a wider strong inversion region at 150K resulted in a lower 1/f noise and insignificant body effect. The analysis of this behavior in 40-nm devices may assist in determining the optimal device fabrication methods and circuit design.

Optimization and Quality Estimation of Circuit Design via Random Region Covering Method

Random region covering is a global optimization technique that explores the landscape by introducing multiple random starting points to initiate the local optimization solvers. This study applies the random region covering technique to circuit design automation and proposes a theory to explain why this technique is efficient at searching for the global optimum. In addition to analyzing the efficiency of the random region covering algorithm, the theory gives a probability-based estimation of the goodness of the optimization result. To enhance the efficiency of the random region covering technique, this work evaluates the boundary of top performance regions and proposes a modified random region covering method that only performs the global optimization on the top design region. The results from a large number of mathematical experiments verify the proposed methodology. The optimized designs of a class-E power amplifier and a wide load range operational amplifier outperform both manual designs and other state-of-the-art optimization techniques.

Telescopic Op-Amp Optimization for MDAC Circuit Design

An 8-bit 40-MS/s low power Multiplying Digital-to-Analog Converter (MDAC) for a pipelined-to-Analog to Digital converter (ADC) is presented. The conventional dedicated operational amplifier (Op-Amp) is performed by using telescopic architecture that features low power and less-area. Further reduction of power and area is achieved by using multifunction 1.5bit/stage MDAC arch itecture. The design of the Op-Amp is performed by the elaboration of a program based on multi objective genetic algorithms to allow automated optimization. The proposed program is used to find the optimal transistors sizes (length and width) in order to obtain the best Op-Amp performances for the MDAC. In th is study, six performances are considered, direct current gain, unity-gain bandwidth, phase margin, power consumption, area, slew rate, thermal noise, and signal to noise ratio. The Matlab optimization toolbox is used to implement the program. Simulations were performed by using Cadence Virtuoso Spectre circuit simulator in standard AMS 0.18μm CMOS technology. A good agreement is observed between the results obtained by the program optimization and simulation, after that the Op-Amp is introduced in the MDAC circuit to extract its performances.

Analog/RF performance of L- and U-shaped channel tunneling field-effect transistors and their application as digital inverters

The inverter performance comparisons of L- and U-shaped channel tunneling field-effect transistors (LTFET and UTFET) are investigated by using Sentaurus TCAD tool. The RF figures of merit for these two TFETs are analyzed in terms of transconductance (gm), output conductance (gds), gate capacitance (Cgg), gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), unit-gain cut-off frequency (fT), the maximum frequency of oscillation (fMAX) and gain bandwidth product (GBW). The simulation results reveal that LTFET and UTFET have the similar DC characteristic due to the identical tunneling process. And the better RF performance LTFET provides due to it has the much smaller Cgd than UTFET. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of inverter circuit implemented with LTFET and UTFET for the first time. And the calculated results demonstrate LTFET is more optimization for inverter circuit design in the novel generation transistors. And all the simulation results in this paper can be used as a reference to choose the characteristic parameters of novel TFETs for inverter applications.

Degradation of the chlorophenoxyacetic herbicide 2,4-D by plasma-ozonation system

A novel advanced oxidation process based on the combination of ozonation with non-thermal plasma generated in a pulsed corona discharge was developed for the oxidative degradation of recalcitrant organic pollutants in water. The pulsed corona discharge in contact with liquid, operated in oxygen, produced 3.5mgL−1 ozone, which was subsequently introduced in the ozonation reactor. The solution to be treated was continuously circulated between the plasma reactor and the ozonation reactor. The system was tested for the degradation of 2,4-dichlorophenoxyacetic acid (2,4-D) and considerably improved performance as compared to ozonation alone, both with respect to the removal of the target compound and to mineralization. The apparent reaction rate constant for 2,4-D removal was 0.195min−1, more than two times higher than the value obtained in ozonation experiments. The mineralization reached more than 90% after 60min treatment and the chlorine balance confirms the absence of quantifiable amounts of chlorinated by-products. The energy efficiency was considerably enhanced by shortening the duration of the discharge pulses, which opens the way for further optimization of the electrical circuit design.

A trust region approach with multivariate Padé model for optimal circuit design

ABSTRACTSince the optimization process requires a significant number of consecutive function evaluations, it is recommended to replace the function by an easily evaluated approximation model during the optimization process. The model suggested in this article is based on a multivariate Padé approximation. This model is constructed using data points of , where is the number of parameters. The model is updated over a sequence of trust regions. This model avoids the slow convergence of linear models of and has features of quadratic models that need interpolation data points of . The proposed approach is tested by applying it to several benchmark problems. Yield optimization using such a direct method is applied to some practical circuit examples. Minimax solution leads to a suitable initial point to carry out the yield optimization process. The yield is optimized by the proposed derivative-free method for active and passive filter examples.

Towards Analog Design Automation using Evolutionary Algorithm: A Review

Analog circuits are the most important parts in many Integrated Circuit (IC) design. This paper reviews the basic concepts in analog design automation using evolutionary algorithm. Analog design problem is a multi objective problem; this can be solved by Evolutionary computation methods. Computation methods provide the set of feasible solutions for the optimal circuit design of analog integrated circuits. It is necessary to integrate both analog and digital in a single chip for real world communication. Due to system level integration we need analog design automation tool for IC design. This paper summarized recent start of art in analog optimization and also lists the survey of main people working in this field. Finally, we listed several open research problem to improve the analog design automation for analog IC using evolutionary computation.

Generalizing block LU factorization: A lower–upper–lower block triangular decomposition with minimal off-diagonal ranks

We propose a novel factorization of a non-singular matrix P, viewed as a 2×2-blocked matrix. The factorization decomposes P into a product of three matrices that are lower block-unitriangular, upper block-triangular, and lower block-unitriangular, respectively. Our goal is to make this factorization “as block-diagonal as possible” by minimizing the ranks of the off-diagonal blocks. We give lower bounds on these ranks and show that they are sharp by providing an algorithm that computes an optimal solution. The proposed decomposition can be viewed as a generalization of the well-known Block LU factorization using the Schur complement. Finally, we briefly explain one application of this factorization: the design of optimal circuits for a certain class of streaming permutations.

A strategy for the identification of optimal flotation circuits

This article presents a strategy for the identification of optimal flotation circuits based on experimental data and the assumption that the flotation circuit structure are not very sensitive to stage recovery. The main objective is to find a set of optimal flotation circuit configurations, including the best metallurgical conditions for the process and cell design. The optimization process maximizes the Net Present Value (NPV). This methodology consists of two steps. The first step of the methodology entails obtaining data from the laboratory. Different metallurgical conditions are tested for different flotation stages. Each metallurgical condition is evaluated to determine its kinetics. The second step of the methodology is the optimization process. The optimization process achieves the best solution by optimizing cell design, flotation circuit structure and metallurgical conditions. The optimization process has three phases. The first phase assumes that every flotation stage has the same residence time and calculates feasible flotation circuits, metallurgical conditions and cell volumes. This process is performed for several residence times and, therefore, a set of feasible solutions is generated. The second phase takes the previous set of feasible solutions and calculates the residence time at each flotation stage. Then, for each phase two solution, the optimal flotation circuit, metallurgical conditions and cell design are calculated. The final product is a set of optimal solutions than can be considered for further study. The procedure is illustrated by the design of a zinc flotation plant, considering seven flotation stages and five species.

Investigation of phosphor-LED lamp for real-time half-duplex wireless VLC system

In this investigation, a 71.3 to 148.4 Mbit s−1 white phosphor-LED visible light communication (VLC) system is proposed and demonstrated under the practical transmission length of 140 to 210 cm. Here, a commercial white-light LED lamp with five cascaded phosphor-LED chips is utilized for illumination and communication simultaneously. In the measurement, we utilize the optical orthogonal frequency division multiplexing quadrature amplitude modulation (OFDM-QAM) with bit-loading algorithm and propose an optimal bias-tee circuit design to improve the modulation bandwidth from 1 MHz to 27 MHz. Moreover, a blue optical filter is not used on the client side. Finally, to realize and demonstrate the real-time transmission performance in the proposed LED VLC system, a commercial OFDM-based digital signal processor (DSP) chip is utilized on the LED lighting side and client side, respectively. Hence, the proposed real-time half-duplex VLC transmission could achieve the 70 Mbit s−1 downstream and upstream data throughputs, under a practical transmission length of 200 cm.

Practical Approximation of Single-Qubit Unitaries by Single-Qubit Quantum Clifford and T Circuits

We present an algorithm, along with its implementation that finds T-optimal approximations of single-qubit Z-rotations using quantum circuits consisting of Clifford and T gates. Our algorithm is capable of handling errors in approximation down to size $10^{-15}$, resulting in optimal single-qubit circuit designs required for implementation of scalable quantum algorithms. Our implementation along with the experimental results are available in the public domain.

Optimization and Effective analysis of Full Adder Circuit Design in 45nm Technology

Optimization and Effective analysis of Full Adder Circuit Design in 45nm Technology

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100x faster than existing approaches, and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with less than 5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.

Foreword Special Issue on Variation Aware Technology and Circuit Co-Design

Once considered mature and commodity technology, CMOS Si technology keeps revamping itself as a collection of most innovative technologies known to humanity at this given time. Beyond conventional vanilla scale of SiON/Poly planar bulk Si technology, lab-level experiments constantly become manufacturing reality, such as high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> , metal gate, FDSOI, FinFET, and many exotic patterning technologies. This rapid pace of new technology introduction to CMOS technology, however, requires much more sophisticated optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout, and circuit design in a holistic manner enables significant performance improvement while reducing overall power consumption with the least amount of area penalty.