Chopper-stabilized Amplifier Research Articles

A low-noise multipath operational amplifier with Gm-shared ping-pong and ripple averaging techniques

This paper presents a low-noise chopper-stabilized multipath operational amplifier with transconductance (Gm) sharing technique between ping-pong stages and ripple averaging technique. While the chopper stabilization is effective in reducing low-frequency noise and offset, output signals may yet contain ripples caused by the modulated amplifier offset. Several schemes can be implemented to suppress these output ripples; however, they require additional chip area and current consumption. The proposed ripple averaging technique effectively eliminates chopper ripples with very low additional power consumption of switched capacitors. To reduce the power consumption and circuit area, the Gm-shared ping-pong scheme is also proposed. The proposed circuit was implemented using a 0.18-μm CMOS process, with a total current consumption of 121.91 μA, and a supply voltage of 1.8 V. It occupies a chip area of 0.33 mm2 and exhibits an input-referred offset of 4.833 μV with a standard deviation 0.861 μV. The proposed amplifier has the input-referred noise level of 20.1 nV/√Hz.

A LFP/AP Mode Reconfigurable Analog Front-End Combining an Electrical EEEG-iEEG Model for the Closed-Loop VNS.

This article presents a local field potential (LFP)/action potential (AP) mode reconfigurable analog front-end (AFE) dedicated for the closed-loop vagus nerve stimulator (VNS). It combines an inverse electrical model of the intracranial electroencephalogram (iEEG) conducting in the brain tissues and been recorded at scalp as the extended electroencephalogram (EEEG). The AFE contains a LFP/AP mode reconfigurable EEEG preamplifier, a tunable integrator to compensate the effect of either the recording electrodes or head tissues, and an adder. The LFP/AP mode reconfigurable EEEG preamplifier consists of a tunable chopper-stabilized amplifier (CSA) and a 2nd-order tunable low pass filter (LPF). For better separation of LFP and AP signals, a high-order DC servo loop (DSL) characterized as a 2nd-order DSL in parallel with a 1st-order DSL is exploited in the tunable CSA to achieve a tunable high-pass frequency with a stopband attenuation slope (SAS) of +40 dB/dec. In addition, the tunable LPF can obtain a tunable low-pass frequency with a SAS of -40 dB/dec and provide additional 20 dB gain for AP signals. Fabricated in a SMIC 180 nm CMOS technology, and in the LFP band (0.5 Hz-200 Hz) and AP band (300 Hz-5 kHz), the measured mid-band gains of the LFP/AP mode reconfigurable EEEG preamplifier are 39.6 dB and 59.5 dB, the input-referred noises (IRNs) are 2.2 μVrms and 6.3 μVrms, the DC/in-band input impedances are 1.27/1.26 GΩ and 0.3/0.22 GΩ, respectively. The power consumption per channel AFE is 6.3 μW, and the die area is 1.4 mm × 0.25 mm.

Design of a 0.5 V Chopper-Stabilized Differential Difference Amplifier for Analog Signal Processing Applications.

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth.

An Energy-Efficient Small-Area Configurable Analog Front-End Interface for Diverse Biosignals Recording.

We introduce a fully integrated configurable analog front-end (CAFE) sensor intended to accommodate various types of bio-potential signals in this article. The proposed CAFE is composed of an AC-coupled chopper-stabilized amplifier to effectively reduce 1/f noise and an energy- and area-efficient tunable filter to tune this interface to the bandwidth of various specific signals of interest. A tunable active-pseudo-resistor is integrated into the amplifier's feedback to realize a reconfigurable high-pass cutoff frequency and enhance its linearity, while the filter is designed using a subthreshold-source-follower-based pseudo-RC (SSF-PRC) topology to attain the required super-low cutoff frequency without the need for extremely low biasing current sources. Implemented in TSMC 40 nm technology, the chip occupies an active area of 0.048 [Formula: see text] while consuming 2.47 μW DC power from a 1.2-V supply voltage. Measurement results indicate that the proposed design achieved a mid-band gain of 37 dB, with an integrated input-referred noise ( VIRN) of 1.7 μVrms within 1-260 Hz. The total harmonic distortion (THD) of the CAFE is below 1 % with a 2.4 m Vpp input signal. With a wide-range bandwidth adjustment capability, the proposed CAFE can be used in both wearable and implantable recording devices to acquire different bio-potential signals.

A chopper amplifier with a pseudo MOS resistor-based tunable bandwidth for EEG applications

PurposeThe purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.Design/methodology/approachThis paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.FindingsThe total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.Research limitations/implicationsAll kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.Practical implicationsThe proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.Originality/valueThe high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

A Chopper-Stabilized Amplifier With a Relaxed Fill-In Technique and 22.6-pA Input Current

In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is mainly due to finite amplifier bandwidth, which causes signal-dependent output spikes at the chopping transitions. Such chopper-induced IMD can be mitigated by the fill-in technique, which involves ping-ponging between the outputs of two identical OTAs chopped in quadrature, thus generating a spike-free output. In this work, a relaxed implementation is proposed in which the output of a fill-in OTA is only briefly used to avoid the spikes of a chopped main OTA. As a result, the fill-in OTA does not need to be chopped, and so it can be duty-cycled to save power. Furthermore, the chopper ripple caused by the main OTA can now be suppressed by a single low-noise ripple-reduction loop, rather than the two AZ loops required in a previous ping-pong implementation of the fill-in technique. Compared to the latter, the proposed amplifier achieves similar IMD performance (-125.7dB), a 25× lower input current (22.6pA) and a flat noise floor (12 nV/Hz).

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection.

This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.

Low-Noise Resistive Bridge Sensor Analog Front-End Using Chopper-Stabilized Multipath Current Feedback Instrumentation Amplifier and Automatic Offset Cancellation Loop

Resistive bridge sensors are used in many application areas to measure changes in physical parameters. To amplify the resistive changes from sensing elements with high precision, various offset contributors in the resistive bridge and amplifiers should be minimized. This study proposes a low-noise resistive bridge sensor analog front-end (AFE) using a chopper-stabilized multipath current feedback instrumentation amplifier (CFIA) and an automatic offset cancellation loop. The proposed circuit exploits a multipath chopper-stabilized architecture for obtaining low noise performance and wide bandwidth characteristics. This circuit can minimize the offsets in the bridge and the high frequency and low frequency amplifiers, while achieving high precision resistive signal acquisition. The high frequency path of the multipath amplifier uses the CFIA topology with class-AB output stage. The offset in the high frequency path is stabilized by the low frequency path amplifier with a high gain and low noise chopper amplifier. The up-modulated offset in the low frequency chopper amplifier path is reduced by the AC-coupled ripple reduction loop (RRL). An automatic offset calibration loop (AOCL) circuit was designed to calibrate the offset due to the bridge mismatch. The AOCL reduces the bridge offset using a successive approximation register (SAR)-based binary-search algorithm. The gain of the proposed circuit is adjustable from 15.56 dB to 44.14 dB. The AFE is implemented in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~ \boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> CMOS process and draws <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$123~ \boldsymbol {\mu } \text{A}$ </tex-math></inline-formula> current from a 3.3 V supply. The input referred noise and noise efficiency factor (NEF) are 14.6 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\surd } $ </tex-math></inline-formula> Hz and 6.1, respectively.

A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers

In chopper amplifiers, the interaction between the input signal and the chopper clock can give rise to intermodulation distortion (IMD). This chopper-induced IMD is mainly due to amplifier delay, which causes large pulses at the output of the amplifier’s output chopper. This article proposes the use of a so-called fill-in technique to eliminate these pulses, and thus the resulting IMD, by multiplexing the outputs of two identical amplifiers that are chopped in quadrature. A prototype chopper-stabilized amplifier was implemented in a 180-nm CMOS process. Measurements show that the fill-in technique suppresses chopper-induced IMD by 28 dB, resulting in an IMD of −126 dB for input frequencies near 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{\mathrm {CH}}$ </tex-math></inline-formula> (=80 kHz). It also improves the amplifier’s two-tone IMD (with 79 and 80 kHz inputs) from −97 to −107 dB, which is the same as that obtained without chopping.

A 108 dB DR Δ∑-∑M Front-End With 720 mVpp Input Range and &gt;±300 mV Offset Removal for Multi-Parameter Biopotential Recording

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2nd-order hybrid-CTDT - modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional modulator, while employing an extra -stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18 μm CMOS process and achieves a peak SNR of 105.6dB and a dynamic range of 108.3dB, for a maximum input range of 720 mVpp. The measured input-referred noise is 0.98 Vrms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

A 2.3-μW Capacitively Coupled Chopper-Stabilized Neural Amplifier With Input Impedance of 6.7 GΩ

Recording electrical activities through high-density electrodes using neural amplifiers plays a crucial role in the successful implementation of a data acquisition system targeting deep-brain regions. To advance the concept of high-density electrodes, neural amplifiers with not only minimum area but also high-power efficiency are needed. This letter presents a neural recording chopper amplifier using the auxiliary path and gain revision techniques to boost the input impedance to a dc value of 6.7 GΩ that meets the requirements of an implantable multichannel recording system. The front-end fabricated in 180-nm CMOS technology occupies an area of 0.051 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes a total power consumption of 2.1 μW drawn from a 1-V supply. The proposed work increases the dc input impedance ( 18×) and decreases the area by 25% in comparison with conventional auxiliary path impedance boosting with a CMRR of -75 dB, and the input-referred noise of 2.1 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> rms</sub> .

A Low-Noise Chopper Amplifier with Offset and Low-Frequency Noise Compensation DC Servo Loop

The low-frequency and low-amplitude characteristics of neural signals poses challenges to neural signals recording. A low noise amplifier (LNA) plays an important role in the recording front-end. A chopper-stabilized analog front-end amplifier (FEA) for neural signal acquisition is presented in this paper. It solves the noise and offset interference caused by the servo loop in the chopper amplifier structure. The proposed FEA employs a switched-capacitor (SC) integrator with offset and low-frequency noise compensation. Moreover, a dc-blocking impedance is placed for ripple-rejection (RR), and a positive feedback loop is employed to increase input impedance. The proposed circuit is design in a 0.18-µm 1.8-V CMOS process. It achieves a bandwidth of up to 9 kHz for local field potential and action potential signals acquisition. The referred-to-input (RTI) noise is 0.72 µVrms in the 1 Hz~200 Hz frequency band and 3.46 µVrms in the 200 Hz~5 kHz frequency band. The noise effect factor is 0.43 (1 Hz~200 Hz) and 2.08 (200 Hz~5 kHz). CMRR higher than 87 dB and PSRR higher than 85 dB are achieved in the entire pass-band. It consumes a power of 3.96 µW/channel and occupies an area of 0.244 mm2/channel.

A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes

The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 upmu hbox {W} at a 1.2 hbox {V} supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 upmu hbox {V}_{mathrm{rms}} in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 hbox {mm}^2 without pads.

A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

A Chopper-Stabilized Amplifier With a Tunable Bandwidth for EEG Acquisition Applications

A chopper-stabilized amplifier for bio-potential signal acquisition applications is presented. The proposed design includes an AC-coupled chopper-stabilized amplifier to reduce the 1/f noise and a tunable MOS-capacitor and a tunable pseudo-resistor to control the bandwidth. It employs a positive feedback input impedance boosting loop (IBL) to increase the input impedance and common-mode rejection ratio (CMRR). The proposed amplifier is designed and fabricated using a Magnachip/SK Hynix $0.18~\mu \text{m}$ 1 poly-6 metal CMOS process and tested with a DC supply voltage of 1.5 V ( $V_{\mathrm {DD}}$ of 0.75 V and $V_{\mathrm {SS}}$ of −0.75 V). The proposed amplifier achieves a midband gain of 47.6 dB, a CMRR of 105.6 dB, and an input-referred noise power spectral density (PSD) of $120~\text{nV}/\surd\text{Hz}$ at 100 Hz with a total power dissipation of 855 nW. The noise-efficiency-factor (NEF) of the proposed amplifier is 2.91. The low-pass corner frequency can be tuned from 200 to 500 Hz. The chip area of the proposed amplifier is 0.065 mm2.

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 $\mu \textrm {V}_{\mathrm {rms}}$ and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5–3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies 25 mm2. Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

Low noise chopper-stabilized instrumentation amplifier with a ripple reduction loop

This paper presents a low noise and residual offset chopper-stabilized precision instrumentation amplifier intended for use in measurement systems. Conventional chopper-stabilized instrumentation a...

A 1.2 V Low-Power CMOS Chopper-Stabilized Analog Front-End IC for Glucose Monitoring

A low-power 1.2 V CMOS chopper-stabilized analog front-end integrated circuit (IC) for glucose monitoring is presented in this letter. The operating parameters of the IC, including reference voltage in potentiostat, current offset, output gain, and offset, are fully programmable. The IC is fabricated using 0.13- $\mu \text{m}$ CMOS technology, has an active area of $1.4\,\,\text {mm} \times 4.3$ mm, and its power consumption is $30.2~\mu \text{W}$ . Furthermore, a chopper-stabilized open-loop transimpedance amplifier is proposed for low-power and low-noise implementation. The integrated input-referred current noise is 260 pArms with a bandwidth of 100 Hz.