Chopper Stabilization Technique Research Articles

A 5-V 290- $\mu\hbox{W}$ Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8- $\mu\hbox{m}$ CMOS Using a Correlated-Level-Shifting Technique

In this brief, a low-power high-resolution readout front end intended for capacitive sensors is presented, in which the circuit uses correlated-level-shifting (CLS) and chopperstabilization (CS) techniques. CLS is a relatively new switchedcapacitor (SC) technique that is used to reduce errors from finite operational amplifier (op-amp) gain, whereas CS is a classic technique that is used to reduce the adverse effects of dc offset and low-frequency noise associated with the op-amp. In this brief, the capacitive sensor is physically emulated by a pair of on-chip differential variable capacitors that are in the femtofarad range. The proposed front end is designed in a 0.8-μm CMOS technology and consumes 290 μW from a single 5-V supply. The readout circuit achieves a capacitance noise floor of 0.018 aF/√Hz at 400 Hz with a sensitivity of 50 mV/fF.

Development and evaluation of an ultralow-noise sensor system for marine electric field measurements

In this paper, we describe the development of an ultralow-noise sensor system consisting of non-polarizable Ag/AgCl electrodes and a chopper amplifier for detecting marine electric field signals. Ag/AgCl electrodes were fabricated using a constant current density to clean the electrode cores and were then electrolytically chloridized by applying a constant potential. An amplifier was developed using the chopper stabilization (CHS) technique to reduce the 1/ƒ noise and the initial offset. To achieve ultralow-noise performance, we took advantage of newly developed materials in the fabrication of Ag/AgCl electrodes and proposed a residual ripple reduction loop to decrease the modulated noise and the offset of the chopper amplifier. Typical measured noise levels are 0.6nV/rt(Hz) for the Ag/AgCl electrodes and 0.55nV/rt(Hz) for the chopper amplifier at 1Hz. The source resistance between pairs of Ag/AgCl electrodes is approximately 5Ω. The offset potential is typically ±0.1mV with a drift of less than 5μV/day. The chopper amplifier had an offset voltage below 0.2μV with a −3dB bandwidth from 0.01Hz to 40Hz and a variable gain from 80dB to 120dB to achieve a large dynamic range. This sensor system is used for marine electric field measurements with high precision.

MEMS 가속도센서를 위한 CMOS Readout 회로

본 논문에서는 MEMS(Micro Electro Mechanical System) 가속도센서를 위한 CMOS readout 회로를 설계하였다. 설계된 CMOS readout 회로는 MEMS 가속도 센서, 커패시턴스-전압 변환기(CVC), 그리고 2차 스위치드 커패시터 <TEX>${\Sigma}{\Delta}$</TEX> 변조기로 구성된다. 이들 회로에는 저주파 잡음과 오프셋을 감소시키기 위한 correlated-double-sampling(CDS)와 chopper-stabilization(CHS) 기법이 적용되었다. 설계 결과 CVC는 150mV/g의 민감도와 0.15%의 비선형성을 갖는다. 설계된 <TEX>${\Sigma}{\Delta}$</TEX> 변조기는 입력전압 진폭이 100mV가 증가할 때, 출력의 듀티 싸이클은 10%씩 증가하며, 0.45%의 비선형성을 갖는다. 전체 회로의 민감도는 150mV/g이며, 전력소모는 5.6mW이다. 제안된 회로는 CMOS 0.35um 공정을 이용하여 설계하였고, 공급 전압은 3.3V이며, 동작 주파수는 2MHz이다. 설계된 칩의 크기는 PAD를 포함하여 <TEX>$0.96mm{\times}0.85mm$</TEX>이다. This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor <TEX>${\Sigma}{\Delta}$</TEX> modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and <TEX>${\Sigma}{\Delta}$</TEX> modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed <TEX>${\Sigma}{\Delta}$</TEX> modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is <TEX>$0.96mm{\times}0.85mm$</TEX>.

Chopper Stabilized, Low-Power, Low-Noise, Front End Interface Circuit for Capacitive CMOS MEMS Sensor Applications

In this paper, a chopper stabilized fully differential CMOS pre-amplifier circuit is presented. The proposed circuit is designed for sub-atto Farad capacitive CMOS MEMS sensing applications. Chopper stabilization technique is employed to minimize flicker (1/f) noise and offsets in the circuit. The proposed circuit is designed using MIMOS 0.35 μm AMS CMOS 3.3 V technology and simulation results from Cadence Virtuoso Spectre circuit simulator show that the proposed circuit is able to detect capacitance changes ranging from 0.0375 aF to 37.5 fF, attain an input inferred noise of 0.9 nV/√Hz, gain of 18.1 dB at 3-dB frequency of 5.5 MHz with total power consumption of 0.33 mW.

A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

Design of High-SNR CMOS Interface Circuit for Micro-Machined Gyroscope

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.

A 2.5 V 109 dB DR ΔΣ ADC for Audio Application

Abstract— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

Analog Integrated Circuits Design for Processing Physiological Signals

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique

This paper presents a low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique. The comparison of the noise-cancellation ability with the correlated double sampling and chopper-stabilization techniques is demonstrated; also, the noise performance of these cancellation techniques is observed and discussed. Using the proposed technique, the modulator achieves 92 dB of dynamic range and -135 dB of noise floor while consuming 950 ¿W from a 3-V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique.

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0,18-μm CMOS was measured at a 0.6-V supply, and achieved 89-nV/√Hz input referred noise (at 100Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-μW power dissipation at 1-V power supply.

Cancellation of Amplifier Offset and &lt;formula formulatype="inline"&gt; &lt;tex&gt;$1/{f}$&lt;/tex&gt;&lt;/formula&gt; Noise: An Improved Chopper Stabilized Technique

In this brief, a theoretical analysis on the limits of conventional chopper stabilization technique is presented and a solution conceived to improve the amplifier performance is proposed. The expected replicas of the 1/f noise at the chopping frequency and its multiples are attenuated by a modified chopping control. Simulations done by using records of real 1/f noise outputs showed that, by following the proposed approach, the spectrum of the signal is not affected while the 1/f replicas are reduced by more than 40 dB with respect to conventional techniques. The required circuit for the generation of the chopping signal is also described. The resulting overhead with respect to conventional techniques is negligible and fully acceptable.

Low-power CMOS wireless MEMS motion sensor for physiological activity monitoring

In this paper, a short distance wireless sensor node "AccuMicroMotion" for physiological activity monitoring is proposed for detecting motions in six degrees of freedom. System architecture, relevant microstructures, and electronic circuits to implement the sensor node are presented. A three-axis microelectromechanical systems (MEMS) accelerometer and a z-axis gyroscope are designed and fabricated using a new deep-reactive ion-etch CMOS-MEMS process. The interface circuits, an analog-to-digital converter, and a wireless transmitter are designed using Taiwan Semiconductor Manufacturing Company 0.35-/spl mu/m CMOS process, wherein the interface circuits adopt chopper stabilization technique and can resolve a signal (dc to 1 kHz) as low as 200 nV from the microsensors; digitized outputs from the microsensors are transmitted by a 900-MHz amplitude-shift-keying radio-frequency transmitter that delivers a 2.2-mW power to a 50-/spl Omega/ antenna. The system draws an average current of 4.8 mA from a 3-V supply when six sensors are in operation simultaneously and provides an overall 60-dB dynamic range.

CMOS front-end amplifier dedicated to monitor very low amplitude signal from implantable sensors

Describes a low-noise, low-power and low-voltage amplifier dedicated to very low amplitude signal acquisition from implantable electronic devices. Low noise and low DC offset are realized by means of chopper stabilization (CHS) technique. In addition, due to adding a rail to rail input stage, low power supply (1.8V) and wide common mode input range (0-1.8V) are achieved. It features a gain of 51dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56nv//spl radic/(Hz).

A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme

A 20-bit delta-sigma A/D converter is implemented in a 0.6-/spl mu/m CMOS process with a single 5-V supply. It provides a 25-kHz data rate for high-speed dc measurement while maintaining good the performance required for accurate dc measurement such as noise, linearity and drift. The front-end programmable gain amplifier (PGA) allows the user to optimize their system for different input ranges. Offset and finite gain compensation are used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta-sigma converter section, low frequency error reduction is achieved through the use of chopper stabilization technique. A frequency-shaped chopper stabilization scheme is used to alleviate the intermodulation tone problem commonly associated with the use of the fixed rate chopping in delta-sigma modulators. This A/D converter achieves 2.5 ppm RMS noise and 12 ppm INL at gain of one.

A monolithically integrated three-axis accelerometer using CMOS compatible stress-sensitive differential amplifiers

In this paper, the development of a bulk-micromachined CMOS integrated three-axis accelerometer which includes analog signal conditioning circuits is presented. The accelerometer was designed to simplify the signal processing tasks by incorporating a set of circuits for three-axis signal conditioning. This approach resulted in a 25% reduction of the circuit area. Stress-sensitive differential amplifiers (SSDAs) have been used as signal transducers, because they can be conveniently formed in a small area. The sensitivity and resolution of the fabricated devices realized in 8/spl times/8 mm/sup 2/ die area were 192 mV/g and 0.024 g for Z-axis acceleration, and 23 mV/g and 0.23 g for X and Y axis acceleration, respectively. The electrical noise component in the analog CMOS circuits was reduced by using a chopper stabilization technique. It was observed that there is a proper chopping clock frequency range to maximize the noise reduction effect. The noise of the SSDA was found to be related with the characteristics of CMOS differential amplifiers used. Typical temperature coefficient of sensitivity was about -2000 ppm//spl deg/C, which could be reduced to -320 ppm//spl deg/C or less by selecting a proper bias condition.

Stable transistor wide-band D-C amplifiers

Stable d-c amplification is required in many engineering applications. In the past, vacuum-tube circuits have been developed which meet most low drift requirements by utilizing differential amplification, chopper, and chopper stabilization techniques. Transistors offer many inherent advantages such as small size, long life, no filament power, low power dissipation and good reliability, but they in turn present new problems in design and techniques. Since the major source of drift in tube d-c amplifiers is filament power variations, the transistor might seem to have inherent advantages concerning drift. However, the variations of transistor parameters with temperature presents as formidable a problem as vacuum-tube filaments. Stable d-c amplifiers using transistors can be designed and constructed by modifying the basic techniques used in vacuum-tube circuits.