Chip Pad Research Articles

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

Defluxing of Copper Pillar Bumped Flip Chips

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and MEMS to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125µm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased. Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 µm and appears to be promising down to pitches of 40µm. Along with reduced pitches, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost. Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product. Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later. The study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch lower than 15 µm and denser packages including 2.5Ds and 3Ds. The cleaning assessment methodologies employed analytical/functional testing including FTIR, Ion Chromatography, SEM/EDX, Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

High-Density Integration of Ultrabright OLEDs on a Miniaturized Needle-Shaped CMOS Backplane.

Direct deposition of organic light-emitting diodes (OLEDs) on silicon-based complementary metal-oxide-semiconductor (CMOS) chips has enabled self-emissive microdisplays with high resolution and fill-factor. Emerging applications of OLEDs in augmented and virtual reality (AR/VR) displays and in biomedical applications, e.g., as brain implants for cell-specific light delivery in optogenetics, require light intensities orders of magnitude above those found in traditional displays. Further requirements often include a microscopic device footprint, a specific shape and ultrastable passivation, e.g., to ensure biocompatibility and minimal invasiveness of OLED-based implants. In this work, up to 1024 ultrabright, microscopic OLEDs are deposited directly on needle-shaped CMOS chips. Transmission electron microscopy and energy-dispersive X-ray spectroscopy are performed on the foundry-provided aluminum contact pads of the CMOS chips to guide a systematic optimization of the contacts. Plasma treatment and implementation of silver interlayers lead to ohmic contact conditions and thus facilitate direct vacuum deposition of orange- and blue-emitting OLED stacks leading to micrometer-sized pixels on the chips. The electronics in each needle allow each pixel to switch individually. The OLED pixels generate a mean optical power density of 0.25mWmm-2, corresponding to >40000cdm-2, well above the requirement for daylight AR applications and optogenetic single-unit activation in the brain.

New Generation Semi-Automatic Thermosonic Wire Bonder

The physical and technological aspects of wire ball-wedge bonding in the assembly of integrated circuits are considered. The video camera and the pattern recognition system (PRS) of new bonder helps to provide accurate positioning of the bonding tool on the chip pads of integrated circuits. The formation of the loop wire cycle is ensured by the synchronous movement of the bonding head along the Z axis and the working table along the XY axes based on the servo drive. A feature of the bonder is that it can bond all the wire loops of the electronic device according to the pre-recorded program without needing to align the bonding points.

Simulation and reliability testing of leadless package high-temperature pressure sensor

Most of the current SOI high-temperature pressure sensors are packaged in lead bonding, where the gold wire is in direct contact with the bonding bump and filled with silicone oil as a protective medium. Silicone oil expands at high temperatures, limiting the sensor's operating temperature to 150 °C or less. To solve this problem, this paper uses an anodic bonding process to bond borosilicate glass wafers to SOI wafers, which are subsequently filled with conductive silver paste and sintered at a high temperature to avoid direct contact between the leads and the chip pads. The reliability of the leadless package structure under high temperature, high pressure, and random vibration is verified by multi-field coupling stress simulation. High-temperature storage and random vibration tests were conducted according to the application requirements, and the results show that the sensor has good reliability and stability.

Chip Pad Inspection Method Based on an Improved YOLOv5 Algorithm.

Chip pad inspection is of great practical importance for chip alignment inspection and correction. It is one of the key technologies for automated chip inspection in semiconductor manufacturing. When applying deep learning methods for chip pad inspection, the main problem to be solved is how to ensure the accuracy of small target pad detection and, at the same time, achieve a lightweight inspection model. The attention mechanism is widely used to improve the accuracy of small target detection by finding the attention region of the network. However, conventional attention mechanisms capture feature information locally, which makes it difficult to effectively improve the detection efficiency of small targets from complex backgrounds in target detection tasks. In this paper, an OCAM (Object Convolution Attention Module) attention module is proposed to build long-range dependencies between channel features and position features by constructing feature contextual relationships to enhance the correlation between features. By adding the OCAM attention module to the feature extraction layer of the YOLOv5 network, the detection performance of chip pads is effectively improved. In addition, a design guideline for the attention layer is proposed in the paper. The attention layer is adjusted by network scaling to avoid network characterization bottlenecks, balance network parameters, and network detection performance, and reduce the hardware device requirements for the improved YOLOv5 network in practical scenarios. Extensive experiments on chip pad datasets, VOC datasets, and COCO datasets show that the approach in this paper is more general and superior to several state-of-the-art methods.

Selection and Characterization of Photosensitive Polyimide for Fan-Out Wafer-Level Packaging

Fan-out wafer-level packaging (FOWLP) is one of the most popular microelectronics packaging technologies. Redistribution layers (RDLs) are employed to expand chip pads beyond the chip edges. Photosensitive polyimide (PI) is widely used in RDLs fabrication. But it also introduces some issues during the thermal cycling test or highly accelerated stress test, for example, warpage, peeling, blistering, and even cracking. In order to reduce these risks at the materials selecting stage, four common dielectric materials–PI A, B, C, and phenolic resin D were investigated in their thermomechanical properties and surface characteristics. And a design of the experiment on process improvement was conducted. The experimental results show that material A owning excellent elongation exceeding 30%, acceptable curing temperature below 260 °C, and low coefficient of thermal expansion (CTE) at 52 ppm/K is more suitable to be adapted as dielectric in RDLs compared with other materials chosen in this article.

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.

A novel rapid micromotion compensator for high-precision chip bonding manufacturing

Large-stroke high-speed positioning stages play a significant role in microelectronic packaging manufacturing. Considering the problem of Z-axis bonding position error caused by inaccurate positioning, diverse chip pad sizes, and other interfering factors, this study proposes a rapid high-precision compensating method with a micromotion compensator to reduce the positioning error in the Z-axis direction. In the study, the micromotion compensator with a unique piezoelectric-spring structure is designed and implemented on the stage working end. Based on the static force analysis and energy storage/dissipation analysis, the exact extension and retraction amount of the compensator is determined in relation to the spring preload force. From the frequency response analysis, the micromotion compensator can achieve a high-frequency performance with appropriate spring stiffness. Thus, the compensator can loyally react to the positioning error and rapidly output the exact compensating amount for the Z-axis operation. Based on the working principle and characteristics of the compensator, the compensating system is implemented. The experimental results show that the compensator can achieve nanometer precision positioning for the motion stage. The proposed Z-axis working-end compensator is particularly useful in the real-time chip bonding manufacturing process for rapid and accurate positioning.

A Cost-Effective Solution for Testing High-Performance Integrated Circuits

Testing of high-speed integrated circuits that enable 100-Gb Ethernet is a complex and expensive proposition. It becomes increasingly difficult to carry out measurements with probes if the test chip’s pad count is very high. A full-fledged packaging solution to test a chip requires a lot of resources and incurs a considerable cost. Other approaches, such as using flip-chip-on-board, prove to be expensive as well. On-board electrical interconnects, if appropriately designed, can be used with wire-bonded dies to perform high-speed measurements using ordinary methods. This article discusses the design and development of a platform to test a high-speed equalizer chip designed for the 100-Gb/s dual polarization-quadrature phase shift keying-based optical links. It also shows how careful optimization of the test platform addressing the aspects of signal delivery from connectors to chip pads through broadband transmission lines and bond-wire transitions and thermal management facilitates the use of low-cost methods to test high-performance chips. Detailed descriptions of the test platform and its validation using $S$ -parameter measurements and the experimental results with an optical system are also presented.

A VCM Active Actuation Method for Bonding Time Reduction in Chip Packaging Process

The voice coil motor (VCM) is widely adopted in chip packaging to achieve high-speed, large-stroke, and high-precision bonding operations. However, the inertial vibration, induced by high-speed high-acceleration motions, may cause significant impact on the chip pad, and affect the packaging efficiency and quality. To achieve a soft-landing chip contacting, the current method usually adopts a microgap searching area to tolerate the inertial vibration, and a low-speed uniform motion is applied after the bonding head is settled down. In order to improve the operation efficiency and reduce the time used in the searching area, this article presents a VCM active actuation (VAA) method to enable switching to the uniform motion in advance and interfering the inertial vibration through the defined actuation conditions. The actuation moment condition is determined by the direction and energy of the inertial vibration, and the actuation amount condition is determined by the effect of the uniform-motion speed on the soft-landing performance. The VCM can be actuated at the right moment with a proper amount in the inertial vibration process to reduce the vibration and searching time, without affecting the rest low-speed soft-landing operation. Based on the simulations, the VAA method is tested experimentally and validated at different velocities, accelerations, and displacements.

Low-Loss Aerosol-Jet Printed Wideband Interconnects for Embedded Devices

This article presents a hybrid process to fabricate chip-to-board interconnects for microwave and millimeter-wave applications. It is a four-step process: 1) cavities are etched in a copper-backed organic substrate [liquid crystal polymer (LCP)]; 2) active and passive devices are mounted in the cavity using a soldering or adhesive material; 3) spacing between the chip and the cavity edge is filled using a UV curable epoxy; and 4) interconnects are formed between the chip pad and the substrate using aerosol-jet printed silver ink. Cavities in the LCP substrate are etched using a wet process, which is simple to implement and allows parallel processing of multiple cavities. Aerosol printing allows custom patterning of interconnects to achieve good impedance transition between the chip and the transmission lines on the LCP substrate. The filler material and the associated structures are first characterized up to 40 GHz. A 0-dB attenuator is utilized to characterize the interconnect process followed by the demonstration of an embedded amplifier using fully printed transmission lines, RF interconnects, and dc biasing. In addition, aerosol printing is utilized for the rework of damaged interconnects. The proposed embedded active process demonstrated is simple to implement and low-cost and provides an approach to design wideband interconnects. An existing shortcoming of the embedded process is the metal contact to the semiconductor substrate at the edge leading to the formation of a Ag/GaAs Schottky contact, which can be eliminated by depositing a thin dielectric film on the exposed semiconductor region.

Inkjet‐printed interconnects for unpackaged dies in printed electronics

This work details manufacturing processes developed to integrate an unpackaged silicon die onto a paper substrate, as part of constructing a hybrid inkjet-printed paper-based circuit. This integration between rigid components and flexible substrates is beneficial in low-cost applications and capitalises on the advantages of both the well-established integrated circuit technology and the emerging paper-based electronics platforms. A superglue incline at the chip edge formed a ramp for printing the silver interconnects between the paper-based circuit and the chip pads. Two printing protocols are compared, the first a single layer using 5 μm drop spacing, and the second using a 35 μm drop spacing for three layers. An unpackaged RFID tag die is successfully integrated and is presented as proof of concept.

A 6-Bit 0.13 μm SiGe BiCMOS Digital Step Attenuator with Low Phase Variation for K-Band Applications

This paper presents the design and measuring of a 6-bit SiGe BiCMOS digital step attenuator, with a maximum attenuation of 31.5 dB, and with 0.5 dB steps (64 states) that have the lowest RMS amplitude error and a low phase variation. To alleviate the large phase variation of the conventional attenuator at a higher frequency, the proposed attenuator utilizes a phase compensation circuit. The phase compensation circuit consists of a 2nd order low pass phase correction network, stacked in parallel to the switched π/T structure of each attenuation module. An attenuator with a phase compensation network shows a root mean square (RMS) amplitude error less than 0.43 dB, and the RMS insertion phase deviation varying from 1.6° to 4.2° over 20–24 GHz. The measured insertion loss is 21.9 dB and the input P1dB is 14.03 dBm at 22 GHz. Our confidence regarding the obtained results stems from a comparison of simulations, carried out using Cadence Virtuoso, and physical measurements using a network analyzer (also presented). The proposed attenuator’s design has a 0.13 μm SiGe BiCMOS process, with an approximate occupied area of 1.92 × 0.4 mm2 including chip pads.

Exploiting the combination of 3D polymer printing and inkjet Ag-nanoparticle printing for advanced packaging

A rapid advanced packaging concept, consisting of 3D photopolymer printing and Ag nanoparticle printing, was investigated for the construction of a simple radio frequency identification (RFID) package with integrated surface acoustic wave transponder (SAW). An acrylate-type SAW package housing was printed with a multi-jet 3D printer and the corresponding antenna for the wireless read-out was manufactured via inkjet printing of Ag nanoparticle ink. The corresponding Ag structure had a thickness of about 2μm with a sheet resistance of 250mΩsq−1 after the photonic sintering processing. The chip-on-board and flip-chip packaging concepts were pursued for connecting the antenna structure to the chip pads. The SAW package prototype in a flip-chip configuration showed a significant signal to noise ratio (SNR) of about 30dB via antenna-bridged radio frequency link at a moderate distance of 3cm.

Fabrication Of 3D Nanostructured Multielectrode Arrays By Using Thermal Nanoimprint Lithography To Improve Cell Coupling For Low Signaling Neurons

Event Abstract Back to Event Fabrication Of 3D Nanostructured Multielectrode Arrays By Using Thermal Nanoimprint Lithography To Improve Cell Coupling For Low Signaling Neurons Dominique Decker1*, Sven Ingebrandt1, Holger Rabe1, Karl-Herbert Schäfer1 and Monika Saumer1 1 University of Applied Sciences Kaiserslautern, Department of Informatics and Microsystems Technologie, Germany Motivation Recently a lot of effort was done in optimizing MEA technology in order to enhance signal qualities and to improve the coupling with cells in a culture. Recording performances can be improved by either coating the MEA with artificial or biological polymers or by adding three dimensional nanostructures on top of the sensing pad, thus increasing the surface area and ensuring a tight cell electrode coupling by partly engulfing the nanosized MEA features by the cells [1, 2]. Here we present a fabrication process of nanostructured MEA chips based on nanoimprint lithography (NIL) and electroplating. Compared to other nanostructuring techniques, NIL offers the possibility to fabricate a whole set of nanostructures on several chips at the same time in a fast, simple and inexpensive full wafer process. The nanostructured MEA devices will later be used for action potential measurements and drug testing with neurons with relative weak signals, such as those from the enteric nervous system. Materials and Methods Silicon or glass wafers are vapor-deposited with 20 nm titanium and 200 nm gold layers, followed by a 200 nm thin spin-coated layer of a thermal resist. Nanoimprint lithography is performed (figure 1) with a customized silicon master stamp including a broad range of nanostructures with different geometries, diameters and arrangements. After removing the residual layer with reactive ion etching the nanostructures are filled with gold by electroplating. Microfabrication techniques including photolithography, wet chemical etching and chemical vapor deposition steps are needed to define the leads, the sensing areas and the contact pads of the MEA chips. Subsequently the wafer is cut. The separated chips are bonded to a PCB, encapsulated and prepared for cell culture experiments. Results and Discussion Different nanostructures like meanders, lines, pillars and tubes with diameters from 50 nm up to 800 nm, different heights up to 500 nm and variable distances between the structures have successfully been fabricated on gold-coated substrates. By means of overelectroplating it is also possible to create mushroom-like or muffin-like structures. AFM and SEM pictures show a good structure transfer during NIL and a high uniformity of the electroplated nanostructures over the whole wafer (figure 2). Electrochemical characterization of the fabricated structures is done with cyclic voltammetry and electrochemical impedance spectroscopy. As expected the measurements show an increase of the electrochemical active surface area and a reduction of the impedance compared to planar electrodes. First biocompatibility tests with P19 cells also show a good cell electrode coupling. Conclusion The presented fabrication process incorporates an alternative, high throughput, time saving and thus cost-efficient method for the integration of nanostructures on MEA chips. Different nanostructures are investigated to find an ideal combination of shape, dimension and arrangement for enhancing the signal-to-noise ratio. Future work will be based on recordings with living cells where we intend to work with neurons from the enteric nervous system. These experiments will explore which nanostructures are best suited for cell electrode coupling and thus signal detection from this particular cell type.

A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture

This paper presents a fully-integrated wireless bondwire accelerometer using a closed-loop readout interface that effectively reduces the noise from electrical circuits and long-term frequency drifts. The proposed accelerometer was fabricated using 0.18- $\mu{\rm m}$ CMOS technology without micro electromechanical systems (MEMS) processing. To reduce manufacturing errors, the bondwire inertial sensors are wire-bonded on the chip pads, thereby enabling a precisely-defined length and space between sensing bondwires. The proposed wireless accelerometer using a pair of 15.2 $\mu{\rm m}$ and 25.4 $\mu{\rm m}$ bondwires achieves a linear transducer gain of 33 mV/g, bandwidth of 5 kHz, a noise floor of 700 $\mu{\rm g}/\surd{\rm Hz}$ , and 4.5 $\mu{\rm g}$ bias stability. The acceleration data is digitalized by an energy-efficient 10-bit SAR ADC and then wirelessly transmitted in real time to the external reader by a low-power on-off shift keying (OOK) transmitter. The proposed architecture consumes 9 mW and the chip area is 2 mm $\times$ 2.4 mm.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits prior to deployment in beneficial applications. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuit technology implemented with multilayer interconnects intended for prolonged operation in applications at temperatures up to 773K (500 °C). A 50mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C). We tested each of the following devices: Transmission Line Method (TLM) test structure, discrete JFET with a gate length of 6 µm and width of 12 µm, discrete on-chip capacitor of area about 0.5mm2, 3-stage ring oscillator comprising of 12 JFET transistors and 30 resistors, and one open-circuit trace on the sapphire wafer to test leakage of everything up to the die. These devices resided on a single 3mm x 3mm SiC die that was bonded via die-attach paste to a 50mm sapphire wafer “package” with patterned 1µm thick gold traces. The lateral spacing of gold traces on sapphire was 3.175mm. The die attach paste is conductive, providing backside electrical contact necessary for stable device operation. 25µm diameter gold ball/wedge bonds connected chip pads to gold traces on the sapphire wafer, and 250 µm diameter gold wires with glass fiber insulation connected the sapphire wafer to a terminal strip outside an oven. The die remained uncovered for the duration of the test. The thermal profile started with a ramp at 3K/minute from 300K to 773K. Then the sample remained at 773K for 22 hours. The 22-hour “burn-in” at 773K was performed because significant reductions in leakage have been observed during previous testing at this temperature. The final ramp from 773K to 1150K was at 9K/minute. The JFET and TLM were measured with a digitizing curve tracer, while the capacitor and sapphire wafer leakages were measured with source-measure units. Ring oscillator output was measured with a 10M-Ohm probe AC-coupled to digitizing oscilloscope. The devices were continuously biased, but only measured every 90 seconds during the thermal ramps and every 2 hours during the 773K “burn in.” The 3-stage ring oscillator frequency decreased from ~850 kHz at 773K to ~660 kHz at 1000K with output amplitude that decreased from 130mV to 20 mV. The JFET exhibited saturation current of 280 µA at 300K that decreased to 50 µA at 1000K. The n-type TLM exhibited specific contact resistance of less than 4 x 10-4 µÙ cm2 throughout the test, and a sheet resistance of 5 kµÙ/square at 300K that increased to 38 kµÙ/square at 1000K with approximately T2power law behavior. No leakage above open-circuit noise floor was observed from the capacitor at 20V bias until 600K. The leakage increased with temperature until 686K at 378 µA at which point the 20V leakage began to drop even while the temperature was increasing. By the time the capacitor had reached the start of the 773K burn in period the leakage had dropped to ~100 µA. The capacitor had measurable leakage again when heated to above 990K and then the max leakage remained below 100 µA. The sapphire did not have measurable 20V leakage until 850K, which increased to 68 nA at 1000K. Above 1000K all devices started to demonstrate behavior consistent with loss of the backside bias connection. Upon cooling and inspection it was found that the backside contact metal on the die and the gold trace area on the sapphire became transparent where there was die attach paste. There were cracks in the on-chip SiO2dielectric formed from low pressure chemical deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor at the corners of some metal traces. Some of the gold ball bonds wires had melted. The peak oven temperature reached 1150K before the oven was turned off so a clear sequence of causality is hard to determine; therefore, electrical data reported is only to 1000K corresponding to apparent loss of backside bias.

Electrical and mechanical properties of RFID chip joints assembled on flexible substrates

Purpose – The purpose of this paper is to examine electrical and mechanical properties of radio frequency identification (RFID) chip joints assembled on a flexible substrate and made from isotropic conductive adhesives (ICAs) reinforced with graphene nanoplatelets (GPNs) or graphite nanofibers (GFNs). Design/methodology/approach – The ICAs reinforced with GPNs or GFNs were prepared and screen printed on a test pattern to investigate resistance and thickness of these adhesive layers. Differential Scanning Calorimetry (DSC) was performed to assess a curing behaviour of the prepared ICAs. Then, RFID chips were mounted with the prepared ICAs to the pattern of silver tracks prepared on foil. Shear test was carried out to evaluate mechanical durability of the created chip joints, and resistance measurements were carried out to evaluate electrical properties of the tested ICAs. Findings – The 0.5 per cent (by weight) addition of GFNs or GPNs to the ICA improved shear force values of the assembled RFID chip joints, whereas resistance of these modified adhesives increased. The DSC analysis showed that a processing temperature of the tested adhesives may range from 80 to 170°C with different curing times. It revealed a crucial influence of curing time and temperature on electrical and mechanical properties of the tested chip joints. When the chip pads were cured for too long (i.e. 60 minutes), it resulted in a resistance increase and shear force decrease of the chip joints. In turn, the increase of curing temperature from 80 to 120°C entailed improvement of electrical and mechanical properties of the assembled chips. It was also found that a failure location changed from the chip – adhesive interface towards the adhesive – substrate one when the curing temperature and time were increased. Research limitations/implications – Further investigations are required to examine changes thoroughly in the adhesive reinforced with GFNs after a growth of curing time. It could also be worth studying electrical and mechanical properties of the conductive adhesive with a different amount of GFNs or GPNs. Practical implications – The tested conductive adhesive reinforced with GFNs or GPNs can be applied in the production of RFID tags because it may enhance the mechanical properties of tags fabricated on flexible substrates. Originality/value – Influence of GFNs and GPNs on the electrical and mechanical properties of commercial ICAs was investigated. These properties were also examined depending on a curing time and temperature. New conductive materials were proposed and tested for a chip assembly process in fabrication of RFID tags on flexible substrates.

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.