Chip Package Research Articles

Reliable Solder Columns to Replace Solder Balls in Large 2.5D Heterogeneous Packages

Solder balls are well suited for interconnecting normal sized ball grid array (BGA) components to printed circuit boards (PCB). However, solder balls are prone to cracking (failure) caused by excessive stresses inherently found in advanced packaging such as large-sized heterogeneous 2.5D packages where multiple dies are placed side-by-side. The growth trend is to make larger and larger BGA processors exceeding 60x60mm in size for AI and data centers. A plethora of new processor substrate and interposer designs are coming on line such as Chip-on-Wafer-on-Substrates (CoWoS). For that reason, more instances of solder ball delamination and cracking on large-sized BGA packages are probable. Solder columns were produced more than 50 years ago to reduce cracking in large ceramic packages, especially for use in harsh environments found in aerospace and defense applications. However, such legacy solder column technology is limited to Tin-Lead (SnPb) alloys. The challenge is to make Lead Free solder columns that satisfy demand for RoHS compliance, while still providing adequate stress relief (compliancy) for extending the operational life of large sized heterogeneous 2.5D processors for mission critical applications. This paper describes our ongoing work to innovate non-collapsible, compliant Lead-Free Braided Copper Solder Columns to reduce strain caused by the Coefficient of Thermal Expansion (CTE) mismatch between large BGA packages and FR4 PCBs. A braid, consisting of 16 fine copper alloy wires, serves as an exoskeleton sleeve around a solder column to provide mechanical support as well as compliancy. This novel solder column technology supports market trends to scale up the size of chip packaging while maintaining reliability. Our focus was to quickly characterize Lead-Free solder column core materials and braiding alloys by employing “Fail-Fast” destructive accelerated mechanical bend testing in our lab. Since there is an ongoing interest in Tin-Lead alloys, this paper also discusses data on Tin-Lead alloys for comparative purposes.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

Cost Analysis of Fan-out Processes for Chiplet Packaging

When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that must be understood, because even if all design requirements can be met, the chiplet package will not come to fruition if the total cost is too high. The basic tradeoff between a monolithic die and a series of chiplets is a reduction in silicon costs countered by an increase in packaging costs. This analysis will compare a monolithic die flip chip package to two fan-out processes that support chiplet packaging. In the first scenario, a two-chiplet chip-last fan-out on substrate package will be compared to a standard flip chip package. For the second comparison, a monolithic flip chip package will be compared to a four-chiplet fan-out package that utilizes embedded silicon for additional interconnect. For both scenarios, a detailed cost comparison will be provided. Activity based cost modeling will be used for this analysis. In addition to looking at the direct costs of the substrated and assembly processes, yield considerations and the prices of the incoming silicon (which varies by node) will be included. The goal of this analsysis is to evaluate the cost of monolithic flip chip package versus a chiplet scenario for two designs, and to highlight the cost drivers of the fan-out chiplet packaging processes.

Study on the Forming Process and Properties of AlSi60 Alloy by Selective Laser Melting

Hypereutectic Al-Si alloys, which have a silicon content ranging from 12% to 70%, are a new generation of casing materials for chip packaging. They have broad applications in aerospace, weaponry, and civilian communications. Selective Laser Melting (SLM) offers significant advantages in achieving near-net shaping of complex casings. This paper presents a study on the formation defects, microstructure, and room temperature tensile properties of AlSi60 alloy prepared by SLM. The results indicate that the primary forming defects in the SLM AlSi60 alloy are balling, lack of fusion, and porosity. These defects are mainly influenced by the volumetric energy density. Samples of good quality can be produced within the range of 150 J/mm3 to 250 J/mm3. However, the same volumetric energy density can result in differences in sample quality due to various combinations of process parameters. Therefore, it has been determined that a well-formed AlSi60 alloy can be obtained within a laser power range of 300 W–350 W, scanning speed of 400 mm/s–800 mm/s, and hatch spacing of 0.09 mm–0.13 mm, with a density close to 98%. The microstructure of the SLM AlSi60 alloy consists of primary Si phases with irregular shapes and sharp edges measuring 5–10 μm, eutectic Si particles of 0.5 μm, and α-Al phases, with eutectic Si dispersed within the α-Al. The SLM AlSi60 alloy exhibits fine and evenly distributed primary Si phases with an average hardness of 203 HV. No significant anisotropy in hardness values was observed in the X and Y directions. The tensile strength of the alloy reached an average of 219 MPa, with an average elongation of 2.99%. During the tensile process, cracks initiated by the primary Si phases rapidly expanded, exhibiting minor ductile fracture characteristics in the Al phases. Due to the high volume fraction of Si phases, the tensile test was dominated by brittle fracture. The tensile curve only exhibited the elastic stage.

A strategy to improve the thermal fatigue resistance of solder joints based on amorphous Co-P coating to spontaneously build skeleton of CoSn3 laths

Integrated circuit systems are always suffering the temperature cycling environment caused by frequent power on and off. Mismatch in thermal expansion coefficients among chip package components will cause severe cyclic stress to the solder joints. During thermal fatigue, β-Sn grains tended to generate thermal fatigue cracks at the grain boundaries. This work proposed a strategy of using amorphous Co-15 at.% P coating as the interface layer to inhibit the initiation and propagation of thermal fatigue cracks and improve the shear strength of solder joints by numerous endogenous CoSn3 laths. Mechanistically, based on the amorphous structure of the Co-P coating, Co atoms would massively and rapidly diffuse into the molten solder during the liquid-solid diffusion stage of reflow soldering, and the eutectic solidification together with β-Sn spontaneously precipitated numerous laths of CoSn3 intermetallic compounds (IMC), which were evenly distributed and became the skeleton of the solders. The skeleton-like CoSn3 laths with high elastic modulus were the reinforcing phase of Sn-based solder, but also refined the grains of β-Sn. The refinement of β-Sn grains and the strengthening of CoSn3 laths played an important role in inhibiting the initiation and propagation of thermal fatigue cracks. In addition, a discontinuous Co-Sn IMC layer was formed between the amorphous Co-P and the solder. The alternating appearance of CoSn3 and relatively soft β-Sn at the interface avoided the generation of cracks at the interface during temperature cycling.

Low-Temperature Atmospheric Pressure Plasma Jets and their Applications in the Surface Activation of some Polymeric Substrates for Advanced Electronic Packaging

The present study applied low-temperature atmospheric plasma (LTAPP) jets to modify polymer substrates used in chip packaging. These substrates include bismaleimide triazine (BT), polyimide (PI) and PTFE materials. All these materials play important roles in modern semiconductor packaging. During the study, focuses were aimed the effects of reactive species (mainly OH and atomic oxygen) generated by atmospheric plasma jets on surface energy, water contact angle (WCA) and surface composition of these three substrates. In order to better understand and apply LTAPP jets, another focus will be on the understanding of the relationship among (1) the generation and distribution of various reactive species, (2) parameters for generating LTAPP jet, and (3) plasma characteristics. The plasma activation mechanism of these substrates was also discussed. In addition to plasma generation using AC high-voltage supplies, plasma characterization using optical emission spectroscopy (i.e., analysis of electron density, electron temperature, plasma temperature, and reactive species), XPS and water WCA analysis were used to understand surface activation mechanisms. In sum, Ar and Ar-O2 plasma jets can be used to modify the surfaces of these three substrates, although the latter relies on the generation of O radicals, while the former relies on OH radicals more. According to the results obtained by XPS analysis, the formation of C-O and C=O bond after plasma treatment is the main reason for surface activation in this study.

Mode I Fatigue and Fracture Assessment of Polyimide-Epoxy and Silicon-Epoxy Interfaces in Chip-Package Components.

Semiconductor advancements demand greater integrated circuit density, structural miniaturization, and complex material combinations, resulting in stress concentrations from property mismatches. This study investigates the failure in two types of interfaces found in chip packages: silicon-epoxy mold compound (EMC) and polyimide-EMC. These interfaces were subjected to quasi-static and fatigue loading conditions. Employing a compliance-based beam method, the tests determined interfacial critical fracture energy values, (GIC), of 0.051 N/mm and 0.037 N/mm for the silicon-EMC and polyimide-EMC interfaces, respectively. Fatigue testing on the polyimide-epoxy interface revealed a fatigue threshold strain energy, (Gth), of 0.042 N/mm. We also observed diverse failure modes and discuss potential mechanical failures in multi-layer chip packages. The findings of this study can contribute to the prediction and mitigation of failure modes in the analyzed chip packaging. The obtained threshold energy and crack growth rate provide insights for designing safe lives for bi-material interfaces in chip packaging under cyclic loads. These insights can guide future research directions, emphasizing the improvement of material properties and exploration of the influence of manufacturing parameters on delamination in multilayer semiconductors.

Thermal Conductivity Enhancement of Polymeric Composites Using Hexagonal Boron Nitride: Design Strategies and Challenges.

With the integration and miniaturization of chips, there is an increasing demand for improved heat dissipation. However, the low thermal conductivity (TC) of polymers, which are commonly used in chip packaging, has seriously limited the development of chips. To address this limitation, researchers have recently shown considerable interest in incorporating high-TC fillers into polymers to fabricate thermally conductive composites. Hexagonal boron nitride (h-BN) has emerged as a promising filler candidate due to its high-TC and excellent electrical insulation. This review comprehensively outlines the design strategies for using h-BN as a high-TC filler and covers intrinsic TC and morphology effects, functionalization methods, and the construction of three-dimensional (3D) thermal conduction networks. Additionally, it introduces some experimental TC measurement techniques of composites and theoretical computational simulations for composite design. Finally, the review summarizes some effective strategies and possible challenges for the design of h-BN fillers. This review provides researchers in the field of thermally conductive polymeric composites with a comprehensive understanding of thermal conduction and constructive guidance on h-BN design.

Development of MSME Production of Various Chips in Mekargalih Village, Jatiluhur Purwakarta District Through Branding Training

There are several problems related to MSME with various chips, one of which is the limited technological knowledge of MSME actors in marketing various chips products, and they have not done marketing digitally (online) so they cannot compete with other MSME who have used digital marketing first. This PKM program aims to make MSME, especially MSME with various chips, have attractive product brands and product previews, as well as be a differentiator with products from other MSME. The community service program regarding the Development of MSME Production of Various Chips in Mekargalih Village, Jatiluhur District, Purwakarta Through Branding Training is felt by the community, especially MSME of various chips. raw material for the production of various other chips. Furthermore, this assistance gives a new color to the packaging of various chips for MSME. In addition to economic-based PKM, other supporting activities such as cement alms for ta'lim majlis and donations for orphans, are deeply felt by the community, especially the recipients of compensation from orphans. Hopefully, the sacrifice of the PKM team can be useful for the wider community, especially the community in the Mekargalih village, Jatiluhur sub-district, Purwakarta district, and can be a good charity savings in the hereafter.

X-ray detection of ceramic packaging chip solder defects based on improved YOLOv5

It is of great significance to detect solder defects of ceramic packaging chips by X-ray detection to improve the quality of electronic products. However, the scale of the solder defects varies violently and there are a lot of tiny, dense, and long narrow defects, making it difficult to identify timely and accurately. To solve the issues mentioned above, an improved object detection model based on the YOLOv5 network, namely YOLO-STPN, is proposed in this paper. We add another prediction head to the original model to detect tiny solder defects effectively. In addition, the swin transformer block and convolutional block attention module are integrated into the path aggregation network, which improve the networks’ ability to identify dense and long narrow defects. The positive sample matching mechanism and the complete intersection over union (CIoU) loss are modified to make the model focus on long narrow defects. Experimental results of 10 types of ceramic packaging chips show that the mean average precision at 50 % IoU (mAP50) of YOLO-STPN is 10.05 % higher than the original YOLOv5 on average, while the decrease of frames per second (FPS) is acceptable. The proposed method has high accuracy and speed. Therefore, it is applicable to the real-time detection of chip packaging.

Cohesive Properties of Bimaterial Interfaces in Semiconductors: Experimental Study and Numerical Simulation Using an Inverse Cohesive Contact Approach.

Examining crack propagation at the interface of bimaterial components under various conditions is essential for improving the reliability of semiconductor designs. However, the fracture behavior of bimaterial interfaces has been relatively underexplored in the literature, particularly in terms of numerical predictions. Numerical simulations offer vital insights into the evolution of interfacial damage and stress distribution in wafers, showcasing their dependence on material properties. The lack of knowledge about specific interfaces poses a significant obstacle to the development of new products and necessitates active remediation for further progress. The objective of this paper is twofold: firstly, to experimentally investigate the behavior of bimaterial interfaces commonly found in semiconductors under quasi-static loading conditions, and secondly, to determine their respective interfacial cohesive properties using an inverse cohesive zone modeling approach. For this purpose, double cantilever beam specimens were manufactured that allow Mode I static fracture analysis of the interfaces. A compliance-based method was used to obtain the crack size during the tests and the Mode I energy release rate (GIc). Experimental results were utilized to simulate the behavior of different interfaces under specific test conditions in Abaqus. The simulation aimed to extract the interfacial cohesive contact properties of the studied bimaterial interfaces. These properties enable designers to predict the strength of the interfaces, particularly under Mode I loading conditions. To this extent, the cohesive zone modeling (CZM) assisted in defining the behavior of the damage propagation through the bimaterial interfaces. As a result, for the silicon-epoxy molding compound (EMC) interface, the results for maximum strength and GIc are, respectively, 26 MPa and 0.05 N/mm. The second interface tested consisted of polyimide and silicon oxide between the silicon and EMC layers, and the results obtained are 21.5 MPa for the maximum tensile strength and 0.02 N/mm for GIc. This study's findings aid in predicting and mitigating failure modes in the studied chip packaging. The insights offer directions for future research, focusing on enhancing material properties and exploring the impact of manufacturing parameters and temperature conditions on delamination in multilayer semiconductors.

Simulation on an Advanced Double-Sided Cooling Flip-Chip Packaging with Diamond Material for Gallium Oxide Devices.

Gallium oxide (Ga2O3) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga2O3 devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga2O3 devices was proposed and the overall packaging of Ga2O3 chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga2O3 chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga2O3 chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga2O3 chips, suggesting promising prospects for this advanced packaging structure.

Design of a Ka-Band Heterogeneous Integrated T/R Module of Phased Array Antenna

The central element of a phased array antenna that performs beam electrical scanning, as well as signal transmission and reception, is the transceiver (T/R) module. Higher standards have been set for the integration, volume, power consumption, stability, and environmental adaptability of T/R modules due to the increased operating frequency of phased array antennas, the variability of application platforms, and the diversified development of system functions. Device-based multichannel T/R modules are the key to realizing low-profile Ka-band phased array antenna microsystem architecture. The design and implementation of a low-profile, high-performance, and highly integrated Ka-band phased array antenna T/R module are examined in this paper. Additionally, a dependable Ka-band four-channel T/R module based on Si/GaAs/Low Temperature Co-fired Ceramic (LTCC), applying multi-material heterogeneous integration architecture, is proposed and fabricated. The chip architecture, transceiver link, LTCC substrates, interconnect interface, and packaging are all taken into consideration when designing the T/R module. When compared to a standard phased array antenna, the module’s profile shrunk from 40 mm to 8 mm, and its overall dimensions are only 10.8 mm × 10 mm × 3 mm. It weighs 1 g, and with the same specs, the single channel volume was reduced by 95%. The T/R module has an output power of ≥26 dBm for single-channel transmission, an efficiency of ≥25%, and a noise factor of ≤4.4 dB. When compared to T/R modules based on System-on-Chip (SOC) devices, the RF performance has significantly improved, as seen by an increase in single channel output power and a decrease in the receiving noise factor. This work lays a foundation for the devitalization and engineering application of T/R modules in highly reliable application scenarios.

Si Substrate Backside -An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging

Si Substrate Backside -An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging

Design and optimization of high-precision servo control system in precision positioning technology

Abstract High-precision control technology, as a general technology in the field of manufacturing and assembly, is widely used in high-end manufacturing equipment such as chip packaging equipment and high-speed CNC machining centers. In this thesis, a permanent magnet synchronous motor is used as the actuator motor of a high-precision servo control system, and vector control strategy and sliding mode observer are adopted to study and realize the servo control of permanent magnet synchronous motor based on sliding mode observer. The current, speed, and position simulation experiments of the high-precision servo control method are also carried out to compare the positioning accuracy before and after the use of the servo control method and to study the performance of the method in precision positioning. The experiments prove the correctness and effectiveness of the SMO-based PMSM high-precision servo control method and the current response speed of the servo control in this paper is fast, and the speed and position estimation errors are maintained within 1.6 r/min and 0.15 rad in steady state condition, and within 20 r/min and 20 rad in the sudden-change condition, which is able to contribute to 11.91% and 19.30% of the machine’s X-axis and Y-axis positioning accuracy improvement. The SMO-based PMSM high-precision servo control method has high steady-state accuracy and immunity to disturbances and can be used for the precision positioning of machine systems.

Graphene-Based Absorptive Gasket for Chip Packages With Enhanced Radiation-Suppression and Heat-Dissipation Capabilities

Graphene-Based Absorptive Gasket for Chip Packages With Enhanced Radiation-Suppression and Heat-Dissipation Capabilities

A pixel-wise segmentation method for automatic X-ray image detection of chip packaging defects

A pixel-wise segmentation method for automatic X-ray image detection of chip packaging defects

An Auto Chip Package Surface Defect Detection Based on Deep Learning

An Auto Chip Package Surface Defect Detection Based on Deep Learning

Regulating the valence state of lead ions in lead aluminosilicate glass to improve the passivation performance for advanced chip packaging

Eliminating surface ion contamination, increasing the reverse breakdown voltage and reducing the leakage current are extremely important for semiconductor devices. Herein, we demonstrated that regulating the valence state of lead ions in lead aluminosilicate glass can efficiently improve the performance of glass passivation technique for chip packaging. It was found that heat treatment technique can be utilized to control valence state of lead ions from +4 into +2 in 20PbO-4.8Al2O3-75.2SiO2 (mol%) (PAS) glass powder, which induces transformation of [PbO3] units into stable glass former units of [PbO4] and generates a free state and charge compensator of Pb2+, therefore contributing to a more stable structure and discoloration of glass. As a result, the optical band gap of glass powder was enhanced from 4.1772 to 4.3184, which could significantly improve glass insulation. As a demonstration of chip packaging, PAS glass powder, after heat treatment processing into a paste for the passivation layer of metal–oxide–semiconductor (MOS) structure devices shows a tight and integrated structure and exhibits a lower fixed charge density from 3.97 × 1010cm−2 to 2.73 × 1010 cm−2. This work provides techniques to adjust the structure of glass to enhance the passivation performance of glass for chip packaging.