Chip Layer Research Articles

Dynamic numerical calculation of multi-physics fields in IGBT chip layer based on ETM-PINN

The electric-thermal-mechanical (ETM) multi-physics coupling fields commonly exists in power electronic devices such as insulate-gate bipolar transistor (IGBT), which dominates the evolution of key state variables inside the components. Among them, the junction e and electric potential of the chip layer, as the dependent variables of various lifetime physical models, directly affect its remaining service life and health status. Aiming at the problem that the key physical variables inside the IGBT are difficult to monitor and predict, this paper first integrates and establishes the ETM coupling partial differential equations (PDEs) inside the IGBT, then accordingly proposes an accurate numerical calculation method for coupled physical fields based on ETM-physics-informed neural networks (ETM-PINN).Through relevant simulation verification, it can not only realize the numerical calculation of the chip layer junction temperature and electric potential field without data, but also perform multi-physics predictive calculation with reduced accuracy in the absence of the key coefficients in PDEs. In the presence of additional physical field data, it can also perform data-model fusion calculations to further improve the solution accuracy.

A junction temperature model based on heat flow distribution in an IGBT module with solder layer voids

The presence of voids in a solder layer affects the thermal reliability of an insulated-gate bipolar transistor (IGBT). In this work, the effects of the size and fraction of solder layer voids and the power losses of chips on heat flow distribution, junction temperature and thermal resistance were investigated. It was found that it was difficult for the heat to flow through the voids due to the high thermal resistance of air. Therefore, the heat above the voids could only flow horizontally, and then avoid the voids and move downward in the solder layer and the following layers, leading to a temperature difference in the surface chip layer. An improved junction temperature model based on the heat flow distribution (HD) considering the solder layer voids was established, the horizontal thermal resistance and horizontal heat capacity are introduced to characterize the effect of the solder layer voids, and the parameter extraction method was proposed. The temperature difference on the surface of the module increased with the increase of the void fraction, and when the void fraction increased from 0 % to 40 %, the surface temperature difference increased from 9.591 °C to 109.86 °C. The results showed that the proposed model not only had a higher accuracy in the estimation of the junction temperature compared with the traditional Cauer model and the improved Cauer model, but also monitored the horizontal temperature differences in the chip layer precisely.

Evaluation of Permeable Pavement Systems for Removing Heavy Metals from Stormwater

This study examines a modified permeable pavement system (PPS) for enhanced heavy metal attenuation from stormwater. A laboratory model consisting of six PPS columns has been tested under varying rainfall intensities. The PPS structures are arranged based on the following hypotheses for enhancing heavy metal attenuation: (i) addition of a natural zeolite layer in the subbase for promoting heavy metal attenuation by adsorption and ion exchange; (ii) addition of a bark chip layer as an organic carbon source for promoting biosorption of heavy metals; (iii) maintaining a saturated zone in order to maintain the required humidity level and decrease the level of oxygen for increased biodegradation; and (iv) inclusion of thin sand layers to restrict the transport of oxygen to create an anoxic zone in the PPS and to enhance filtration. Successful treatment of metals such as Ba, Co, Mn, Ni, and Zn has been observed under various rainfall conditions using a conventional PPS. The rainfall intensity greatly influences the attenuation of Al, Cr, Cu, Mo and Sr. During heavy rains through the conventional PPS structure, chromium is found to be leached back into the infiltrate. The results indicate that by changing the subbase material and layer setting, biosorption of heavy metals can be encouraged in the PPS structure. The results of this study suggest that the PPS structure be amended by adding into its subbase a saturated region, an organic carbon donor and thin sand layers for enhanced heavy metal attenuation. Compared to the conventional structure, the proposed structure reduces Cr desorption and improves the attenuation of Al, Cu and Mo.

Comparative Study of the Parameter Acquisition Methods for the Cauer Thermal Network Model of an IGBT Module

Under the operating conditions of high power and high switching frequency, an insulated gate bipolar transistor (IGBT) chip can produce relatively large power loss, causing the junction temperature to rise rapidly; consequently, the reliability of the IGBT module can be seriously affected. Therefore, it is necessary to accurately predict the junction temperature of the IGBT chip. The resistance capacitance (RC) thermal network model is a commonly used method for IGBT junction temperature prediction. In this paper, the model parameters are obtained by two methods to establish the Cauer thermal network models of the IGBT module. The first method is to experimentally obtain the transient thermal impedance curve of the IGBT module and the structure function and then extract the individual thermal parameters of the Cauer thermal network model; the second method is to obtain the thermal parameters of the thermal network model directly by using theoretical formulas that consider the influence of the heat spreading angle. The predicted junction temperatures of the Cauer thermal network models established by the two methods are compared with the junction temperatures obtained from infrared (IR) measurements during the power cycling test, the junction temperatures measured by the temperature-sensitive electrical parameter (TSEP) method, and the junction temperatures calculated by finite element (FE) analysis. Additionally, the Cauer thermal network models established by the two methods are compared and verified. The results indicate that the Cauer thermal network model established based on theoretical formulas can accurately predict the maximum junction temperature of the IGBT chip, and the calculated temperature for each layer, from the IGBT chip layer to the ceramic layer, also accords well with the FE results. The Cauer thermal network model established based on the experimental test and the structure function can accurately predict the average junction temperature of the IGBT chip.

Влияние пластической неустойчивости приконтактных слоев стружки на механизм изнашивания твердосплавного инструмента

The mechanism of plastic deformation of the incised chip layer during cutting of carbon steels and titanium alloy is investigated. It is shown that high degrees of deformation cause melting and the vortex nature of the movement of particles of the processed material in it, causing intensive wear of the carbide tool.

A Temperature-Dependent Cauer Model Simulation of IGBT Module With Analytical Thermal Impedance Characterization

In pursuit of high power density and high reliability of power converters, the junction temperature of power devices becomes an essential indicator for heath condition monitoring and thermal management. Particularly under high-temperature operating conditions, the temperature-dependent thermal properties of the chip and ceramic materials must be incorporated to enhance the prediction accuracy. In this article, an improved temperature-dependent Cauer-type thermal network of insulated-gate bipolar transistor (IGBT) module is established. The temperature dependence of thermal parameters for the chip layer and ceramic layer is meticulously considered. More importantly, finite-element method (FEM) simulation is used to yield the heat flux curve of the power module at the center line in order to better imitate the real heat-spreading scenario. In this way, the effective heat transfer area of each layer can be calculated accurately and analytically. By this analytic method, the temperature-dependent thermal impedance can be efficiently determined. Compared with prior-art fully FEM-based temperature-dependent thermal impedance characterization method, the method proposed in this article reduces the FEM simulation time cost approximately 20 times under the same computing hardware facilities and considerably simplifies the parameter extraction process. Finally, experimental results based on two commercial IGBT modules successfully validate the usefulness, effectiveness, and accuracy of the proposed thermal network model.

Study on surface integrity of titanium alloy machined by electrical discharge-assisted milling

• Electrical discharge-assisted milling (EDAM) can improve the surface integrity of Ti-4Al-6 V. • EDAM can reduce the surface roughness compared with conventional milling (CM). • Compared with CM, the residual tensile stress generated by EDAM is smaller. • The microhardness of machined surface after EDAM is relatively smaller than CM. • Moderate capacitance has more positive influence for surface integrity. Electrical discharge-assisted milling (EDAM) is an efficient machining process for titanium alloys according to previous studies. However, a complete understanding of the surface integrity of titanium alloy machined with EDAM is not yet sufficient. Therefore, in this paper, surface defects such as chip layer adhesion, debris, feed marks, and burrs were investigated and identified. Among them, the adhesion of the chip layer is the most common surface defect and is the factor that has the greatest influence on the surface quality. In addition, surface roughness, micro-hardness, and residual stress were analyzed and discussed. The results show that the surface roughness of EDAM is significantly improved compared to conventional milling (CM). Also, the residual stress generated by EDAM is much smaller than that of CM, and the main type of residual stress is residual compressive stress. Similarly, the surface microhardness after EDAM is also slightly smaller than that of CM. This increased surface integrity is due to the material softening effect due to the heat generated by the discharge spark. Consequently, EDAM is a good candidate method for efficient machining of titanium alloys.

Analysis of hotspots and cooling strategy for multilayer three-dimensional integrated circuits

The effects of geometric and thermal properties of multilayer nominal three-dimensional chip on the temperature hotspots are investigated in this work. Based on heat-transfer computational fluid dynamic analysis, various effective parameters which correlate with reducing the hotspot temperature are studied. A new analytical method for the equivalent thermal conductivity of the thermal interface material (TIM) layer and the chip layer structure in the multilayer chip is proposed, the deviation between the present results and the prior literature is less than 2%. For different chip structures and through silicon vias (TSV) arrangements, the higher the number of multi-layer chips subject to a low Reynolds number, the higher the hotspot temperature. The hotspot temperature gradually decreases linearly with an increase in the Reynolds number. For a convective cooling environment, comparing the two cases with and without the TSV, the variation of Nusselt number for the chip package surface facing the coolant is less than 1. The staggered core structure has a lower hotspot temperature for the no TSV case. When the Core-Centralized TSV is introduced, the overlapping core structure influences the internal heat dissipation the most. When the Reynolds number increases to 2000 and the number of chip layers is greater than 10, the hotspot temperature is almost insensitive to the chip layer and the hotspot temperature difference among different multilayer 3D chips does not exceed 0.2%. The layer where the hotspot temperature exists is different for different TSV arrangements.

Multi-Path Propagation in On-Chip Optical Wireless Links

Optical wireless networks-on-chip (OWiNoC) are considered as a possible solution to overcome the communication bottleneck due to wired interconnects in modern chip multi-processor systems. The efficient implementation of optical wireless links requires considering many different aspects, including analysis and deep understanding of the effects on the propagation of the electromagnetic field induced by the discontinuities that can be found in a realistic scenario. This letter aims at showing the impact determined by some of these discontinuities on optical links designed in Silicon-on-Insulator technology, exploiting simple point-to-point interconnections as a first example. Measurements and simulations confirm that multi-path phenomena, triggered by the multi-layer structure housing the antennas and the propagation paths, can have a serious impact on the link budget, with fading effects that may compromise the performance of the link. However, in the presented experimental results, thanks to a careful choice of the chip layer structure, received powers higher than those which could have been measured for optical links fabricated in an infinite homogeneous medium are observed, thus resulting beneficial for the connection's power budget.

Strain Rate of Metal Deformation in the Machining Process from a Fluid Flow Perspective

Metal cutting speeds are getting faster with the development of high-speed cutting technology, and with the increase in cutting speed, the strain rate will become larger, which makes the study of the metal cutting process more inconvenient. At the same time, with the increase in strain rate, the dislocation movement controlling the plastic deformation mechanism of metal will change from thermal activation to a damping mechanism, which makes the metal deformation behave more like a fluid. Therefore, it is necessary to explore new ways of studying machining from the perspective of fluid flow. Based on this, a fluid model of the metal cutting process is established, and a method for calculating the strain rate is proposed from the point of view of flow. The results of the simulation and measurements are compared and analyzed. The results show that the strain rate on the rake face will be affected by the friction between the chip and tool; the nearer the distance between the chip layer and tool rake face, the bigger the strain rate will be. The strain rate in the central shear plane is much larger than in other areas along the shear plane direction, and in which two ends are the biggest. It can achieve rougher, quantitative research. This shows it is feasible to study machining from the viewpoint of fluid flow, though it still needs a lot of theoretical support and experimental confirmation.

Analytical model of cutting temperature field in workpiece including uncut chip layer

To understand the nature of chip formation in cutting, the study of temperature field in the uncut chip layer of the workpiece is extremely important. In this study, the temperature field for the uncut chip layer is modeled using the heat source projection at different depths of the layer along the cutting speed direction to obtain the different heating times of points at corresponding depths. It is based on the model of the cutting temperature field in the machined surface layer of the workpiece, as proposed in the previous paper of the authors. The temperature distribution in both uncut chip and machined surface layers are thus achieved, and the temperature penetration depths in the machined surface layer are compared with experiment results. The results show that the computed isotherms on the boundary of the uncut chip and machined surface layers are continuous and smooth, indicating that the temperature field model for the uncut chip layer is correct. The temperature field for the nonplanar primary shear plane heat source is also modeled by introducing the curve integral. This is considerably significant in the conduct of further research on the temperature field in micromachining considering size effects and in machining using restricted contact tools, such as groove-type chip breaker tool, double-rake-angled tool, rounded-edge tool, and tool with built-up edge.

Damage mechanisms of polycrystalline aluminate magnesium spinel (PAMS) under different loading conditions of indentation and micro-cutting tests

This paper studies the damage mechanisms of polycrystalline aluminate magnesium (PAMS) under different loading conditions of indentation tests and micro-cutting with various rake angles of the cutting tools. A decreasing trend is confirmed in the hardness values with growing loadings. The observed hardness value approaches a plateau at about 1406–1679 HV. The tardive cracks, which break out spontaneously within a delayed period of time following the end of indentation, are for the first time observed in the indentation experiment of this paper. The tardive crack originates from a crack system containing a lateral subsurface crack with two median cracks on its both sides. These results imply that PAMS can store the unbalanced strain energy induced by the applied loading within the vicinity of the loaded volume which will be released in accordance with the intergranular crack-growing path extending to the surface. In addition, the linear plunge-cutting tests coin the effect of tool rake angle: the tool with a zero rake angle produces poor surface quality with sever surface damages whilst the tools with negative rake angles can improve the ductility of PAMS to a certain extent. However, negative rake angles are proved to be the root cause of median cracks and large spalling fractures. On the contrary, a positive rake angle tool can be applied to reduce the severity of surface damage and confine the damage patterns mainly as small spallings fractures. Besides the experimental study, finite element method (FEM) models are developed to reveal the underlying mechanism of the rake-angle effect on the micro-cutting process. The simulation results visualise the different stress distributions in the uncut areas and prove that a tool with positive rake angle can transfer the stress to the uncut chip layer whereby the damage probability to the machined surface is significantly reduced.

Router-integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems

In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads to maintain sharing data efficiently. In this work, an enhanced router network is integrated within the private cache level for fast interconnecting sharing data accesses existing in different threads. All sharing data in private cache level can be classified into seven access types by experimental pattern analysis. Then, both shared accesses and thread-crossed accesses can be rapidly detected and dealt with in the proposed router network. As a result, the access latency of private cache is decreased, and a conventional coherence traffic problem is alleviated. The process in the proposed path is composed of three steps. Firstly, the target accesses can be detected by exploring in the router network. Then, the proposed replacement logic can handle those accesses for maintaining data coherence. Finally, those accesses are delivered in the proposed data deliverer. Thus, the harmful data sharing accesses are solved within the first chip layer in 3D-IC structure. The proposed system is also implemented into a cycle-precise simulation platform, and experimental results illustrate that our model can improve the Instructions Per Cycle (IPC) of on-chip execution by maximum 31.85 percent, while energy consumption can be saved by about 17.61 percent compared to the base system.

Effects on thermal performance enhancement of pin-fin structures for insulated gate bipolar transistor (IGBT) cooling in high voltage heater system

The thermal performance enhancement of pin-fin structures for IGBT cooling in high voltage heater (HVH) system is numerically investigated and experimentally verified in this study. The results revealed that there may be a risk of thermal failure of the IGBT in existing HVH systems. Additionally, a new heat exchanger was designed with pin-fin structures to enhance heat transfer for cooling the IGBT component. To analyze the influence of pin-fin parameters on the cooling effect, a L16(4̂5) orthogonal array was selected to identify the main and secondary parameters, then the optimal combination scheme was found. The sensitivity analysis result showed that the diameter of the pin-fin had the greatest influence on the amount of heat transfer, and the height of pin-fin is the second. For cooling uniformity, height is the most important parameter and the diameter is the second. The optimization scheme obtained by orthogonal design could simultaneously meet the requirements of heat transfer and cooling uniformity. Compared with the original model, the maximum temperature and the maximum difference of the average temperatures of the IGBT chip layer decreased 9.4% and 14.6%, respectively.

Integrated and Interconnected Array of Light-Emitting Transistors and Transistor Lasers on Silicon for Photonic Logic

A scalable method of integrating III-V epitaxial structures onto silicon and producing a large-area array of interconnected three-terminal photonic devices in the integrated material is demonstrated. This work establishes CMOS-compatible techniques for GaAs-based active photonic material (n-InGaP/p-GaAs/n-GaAs) to be converted into a distribution of epitaxial islands with direct thermal and electrical connection to a silicon host wafer. A temporary epitaxial bonding process orients and etches modified heterojunction bipolar transistor (HBT) material into a gridded mesh of islands (collector-side up) on a silicon-based carrier wafer with device-level alignment. A subsequent epitaxial transfer creates a permanent metal-eutectic bond between the III-V islands and the silicon host wafer that serves as a uniform electrical interconnect between front-end-of-line processed CMOS and the collector terminals of a photonic chip layer. Thermal, electrical, and mechanical characterization of the integrated material is performed to ensure that the interconnect is suitable for fabrication of photonic devices into the larger-area transferred material. A separate epitaxial process for uniting passive waveguide materials to the same host wafer is then similarly performed. The result is a closely-aligned grid where each III-V island is surrounded by passive material islands. The integrated III-V islands (emitter-side up) are then patterned in unison into an array of light-emitting transistors (LET) and edge-emitting transistor lasers (TL) that are designed for efficient optical coupling into waveguides formed in the passive material, functioning together as active and passive devices in a single network. Device processing parameters are inspected and optimized to account for variations in processing on integrated (thin-film) III-V materials as compared to monolithic device processing, as well as to adhere to CMOS-compatible methods and metallization. The resulting array of three-terminal photonic devices are linked by means of a vertical electrical interconnect through the collector contact and a lateral optical interconnect aligned to the carrier-recombination quantum well (QW) in the base region. Optical and electrical testing (DC) is performed on the integrated devices both individually and as an integrated network for electrical and optical output characteristics, while a comparison to fabricated monolithic three-terminal photonic devices is utilized to relate performance of integrated active photonic devices. Initial work on high-speed testing is performed to benchmark the thermal and electrical improvements in integrated photonic devices. Simulation of the device characteristics is further employed to investigate methods to optimize optical output in relation to electrical gain and beta suppression. The techniques and processes established enable a scalable network of photonic devices for novel heterogeneously integrated electronic-photonic circuitry. This heterogeneous integration produces a platform for pairing a photonic chip layer with a CMOS host wafer such that the interconnects for electrical and optical signals allow for photonic logic designs. Figure 1

Practical Partial Hardware Reverse Engineering Analysis

Reverse engineering typically requires expensive equipment, skilled technicians, time, a cross section of the component to be sliced out and a dedicated reconstruction software. In this paper, we present a low-cost alternative, combining fast frontside sample preparation, electron microscopy imaging, error-free standard cell recognition and within and between-die standard cell statistical analysis (SCSA). Step-by-step, we depict the process to access the transistor’s drain/source area, to acquire the full area of a single chip layer, to adapt pattern recognition for standard cells and to analyze the standard cell width, local/global location and occurrences number. The inner workings of each step are accompanied by results on 45–65-nm FCBGA devices enabling to locate specific areas (e.g. registers, hardware accelerator). We particularly point out the importance of such design information extraction for local fault injection and hardware assurance. The primary goal is to analyze how much design information of a complex integrated circuit can be retrieved with minimal costs and without outsourcing.

Comparative study on drilling effect between conventional drilling and ultrasonic-assisted drilling of Ti-6Al-4V/Al2024-T351 laminated material

This paper investigates the performance of ultrasonic-assisted drilling (UAD) in machining of Ti-6Al-4V/Al2024-T351 laminated material by using DEFORM-3D finite element method. The effectiveness of two key parameters, frequency and spindle speed, is discussed. The purpose is to explore the effect of UAD on machining performance, to compare it with conventional drilling (CD) and to prove that the UAD technique could achieve better hole quality. To be more specific, the following aspects are taken into account: chip morphology, layer delamination, thrust force, temperature change, and effective stress. The result shows that UAD can produce fragile chips, smaller layer delamination, lower thrust force, larger maximum temperature, and lower effective stress. Both frequency and spindle speed have influence in their own way on machining process.

An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3-D ICs

Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time-consuming for the drop test simulation, and therefore the fast numerical approach is needed to reduce the computational cost. In this paper, we propose an efficient drop test simulator for through-silicon-via (TSV)-based 3-D IC to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second-order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. Second, an equivalent structure-embedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop test simulator can achieve $7.03\times $ speedup in comparison with the conventional finite-element method-based solver. It is demonstrated in this paper through several examples with multichip layers, of which each chip layer consists of an $8\times 8$ TSV array, that the proposed simulator can be widely applied to reliability analysis of 3-D ICs under drop impact.

An identification model of cutting force coefficients for five-axis ball-end milling

Five-axis ball-end milling is widely used in energy, ship, aerospace, and other fields. As one of the difficulties in milling research, milling force is often critical to the processing efficiency and quality of part. For predicting the milling force of the five-axis ball-end milling better, this paper presents a cutting force coefficients identification model which is related to the instantaneous chip layer thickness and axial position angle considering the cutter run-out. For five-axis ball-end milling of the oblique plane, the relationship of feed direction, cutter axis vector, and machined surface is parameterized. The boundary curves of cutter workpiece engagement (CWE) are determined by intersecting spatial surfaces. The boundary curves are discretized, and an algorithm of in-cut cutting edge (ICCE) is proposed by defining the distance between discrete points and the cutting edge. Combining the instantaneous chip thickness considering arbitrary feed direction and cutter run-out, the five-axis milling force model of ball-end mill is established. Based on the undetermined coefficient method and the instantaneous average milling force of teeth, the cutting force coefficients identification model corresponding to the instantaneous chip layer thickness and the axial position angle is established. Furthermore, cutter run-out parameters are obtained combined with instantaneous measured milling force of single tooth. The experimental and simulation examples demonstrate that the CWE determined by the spatial surfaces is consistent with the experimental results. The ICCE is in good agreement with the simulation results based on the solid modeling method. A large number of milling experiments under different processing parameters show that the cutting force coefficients and cutter run-out parameters identification model can be effectively applied to five-axis ball-end milling.

A modified bidirectional thermal resistance model for junction and phosphor temperature estimation in phosphor-converted light-emitting diodes

Besides the junction temperature, phosphor temperature is another key parameter to characterize the thermal behavior of phosphor-converted light-emitting diodes (pc-LEDs). However, the measurement of phosphor temperature remains a challenge. In this paper, we proposed a modified bidirectional thermal resistance model for the junction and phosphor temperature estimation. Compared with the conventional thermal resistance model, both the heat generation of the phosphor layer and the heat flow through the phosphor layer were further considered in this model. Three LED packaging structures were fabricated and measured to complete the model. The heat generation of the chip and phosphor layer was measured. With varying driving current from 0.05A to 0.65A with an increment of 0.1A, the maximum deviation of the predicted and measured junction and phosphor temperature is less than 1% and 9.2%, respectively, which proves the feasibility of the proposed model for the junction and phosphor temperature estimation.