Analysis of hotspots and cooling strategy for multilayer three-dimensional integrated circuits

Abstract

The effects of geometric and thermal properties of multilayer nominal three-dimensional chip on the temperature hotspots are investigated in this work. Based on heat-transfer computational fluid dynamic analysis, various effective parameters which correlate with reducing the hotspot temperature are studied. A new analytical method for the equivalent thermal conductivity of the thermal interface material (TIM) layer and the chip layer structure in the multilayer chip is proposed, the deviation between the present results and the prior literature is less than 2%. For different chip structures and through silicon vias (TSV) arrangements, the higher the number of multi-layer chips subject to a low Reynolds number, the higher the hotspot temperature. The hotspot temperature gradually decreases linearly with an increase in the Reynolds number. For a convective cooling environment, comparing the two cases with and without the TSV, the variation of Nusselt number for the chip package surface facing the coolant is less than 1. The staggered core structure has a lower hotspot temperature for the no TSV case. When the Core-Centralized TSV is introduced, the overlapping core structure influences the internal heat dissipation the most. When the Reynolds number increases to 2000 and the number of chip layers is greater than 10, the hotspot temperature is almost insensitive to the chip layer and the hotspot temperature difference among different multilayer 3D chips does not exceed 0.2%. The layer where the hotspot temperature exists is different for different TSV arrangements.