Chip Ceramic Ball Grid Array Research Articles

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Estimation of Curing Profile's Parameters for Flip Chip Packaging Using DSC and TGA

This paper presents the method to estimate curing profile's parameters for curing process of Moisture Resistance Cyanate Ester (MRCE) based underfill used in Flip Chip Ceramic Ball Grid Array (FC-CBGA). The two steps curing profile was found to eliminate voids formation in underfill during curing process. The important parameters in two steps curing profile such as first fixed temperature and duration of second temperature rise were estimated by superimposed of cure initiation curve and weight percentage loss curve of underfill epoxy material. Differential Scanning Calorimeter (DSC) analysis was carried out to characterize the cure kinetics reaction of underfill epoxy and produced the cure initiation curve. Thermal Gravimetric Analysis (TGA) was performed to characterize the weight loss of underfill and produced the weight loss curve. It was estimated that the first fixed temperature and duration of second temperature rise for two steps curing profile were 100 oC and 60-80 minutes respectively. The simulation experiment was conducted to verify the profile and no voids formation observed along this curing process.

The Effect of Underfill Fillet Geometry to Die Edge Stress for Flip Chip Packaging

The possible source of die edge cracking for Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA) models were used to analyze the effect of underfill fillet geometry on interfacial stresses between die edge and the underfill fillet. The input parameters of FC-CBGA from industry was used for simulation and the properties of commercial underfill were extracted by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). Die stress distribution for different fillet height were generated to depict variation of stress due thermal loading. The variation of tensile stress due different fillet height and width were discussed for parameters optimization.

An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.

Comparative Study of Different Underfill Material on Flip Chip Ceramic Ball Grid Array Based on Accelerated Thermal Cycling

Problem statement: This study mainly to study the effect of several commercial underfill materials to the reliability of HiCTE Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to Accelerated Thermal Cycling (ATC) effect. Approach: The warpage condition of package, die back stress, interfacial die shear stress, and solder bump fatigue for different commercial underfills were assessed and compared via a commercial Finite Element Analysis (FEA) under JEDEC Standard of ATC. The thermo-mechanical properties of underfills for simulation were obtained by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). The actual package of HiCTE FC-CBGA were assembled with those underfill materials and underwent ATC to be compared with FEA result. Results: The results from FEA and experimental were discussed to characterize the performance of each underfill material. The results of this study indicate that the underfill materials investigated, those with a glass transition temperature (Tg) and a Young’s modulus of approximately above 105°C and 8-9 GPa, respectively, were appropriate for HiCTE FC-CBGA with high lead solder bumps. Conclusion: The result from FEA analysis and ATC reliability test found that the underfill materials with high and medium low Young’s modulus has high reliability in FC-CBGA package.

Thermal analysis of a flip chip ceramic ball grid array (CBGA) package

The function of an electronic cooling package is to dissipate heat to ensure proper operation and reliability. The flip chip ball grid array package is probably the most suitable package for high-level thermal performance applications. A high thermal performance flip chip ceramic ball grid array (FC-CBGA) package with an aluminum silicon carbide (AlSiC) lid and one without lid were evaluated using the computational fluid dynamics (CFD) technique. This paper compares the thermal performance of a 35 × 35 mm FC-CBGA package with three different die sizes of 5 × 5 mm, 15 × 15 mm and 20 × 20 mm. The performance of a lid fitted with different heat sinks was investigated in standard JEDEC defined natural and in forced convection environments. Thermal measurements were performed using a functional application specific integrated circuit (ASIC) chip, in compliance with the JEDEC standards. Excellent agreement was found between the numerical results and the measured data. Improved thermal performance was observed with a lidded package as compared to the unlidded one. However, no significant improvement was observed between lidded and unlidded packages when fitted with a heat sink subjected to forced convection. This paper also discusses the package thermal budget estimate with and without heat sinks. Printed circuit board and package top surface temperature patterns were measured using an infrared thermal camera. The usefulness of the thermal characterization parameter is demonstrated in system level applications. Parametric studies were carried out to understand the effect of die size, radiation effect, gird size variations and airflow rate on die junction temperature and package thermal resistance. This study also incorporates the effects of substrate, lid, die and PCB temperatures for different die sizes in natural and forced convection environments.