Chemical Mechanical Planarization Step Research Articles

Decoding CMP Challenges: A Metrospection Insight

We live in a digitally connected world with Global data to exceed 180 ZB by 2025 per some estimates1. Memory is the fiber connecting our world. New applications drive continued demand growth for memory and storage applications. Micron is a leader in the memory and storage industry, helping the world use information to enrich lives. As memory devices scale and new memory technologies arise, the requirements for Chemical Mechanical Planarization (CMP) processes are becoming tighter and more stringent node over node. Furthermore, memory scaling continues to become more dependent upon CMP, with not only a steady increase in the number of CMP steps but that of unique CMP steps as well node over node. In this presentation we focus on CMP challenges from a METROSPECTION (Metrology & Inspection) lens. We explore the critical role of inspection and metrology techniques in optimizing CMP for semiconductor memory fabrication. The ability and need for the integration of cutting-edge inspection techniques and metrology strategies emerges as a pivotal element in enhancing CMP cycles of learning and hence the reliability, yield, and overall quality of semiconductor memory devices.1 - Statista

Optimizing the Within Wafer Non-Uniformity at the Chemical Mechanical Planarization step in Interposers and RDL fabrication process for 3D IC stacking

Abstract Chemical Mechanical Planarization (CMP) is an integral step in fabrication processes of through silicon via based Interposer and Redistribution layer for routing. The key motivation in the CMP process is to achieve planarization with minimum recess and dishing on the metal routing sites. In this work we established the metrics for Within-wafer non-uniformity (WIWNU) and optimized the CMP parameters. Currently, there is no standard guideline for reporting the WIWNU during CMP and thus a better understanding and practice is needed to enhance post CMP uniformity across the wafer. The work reported in this article were conducted on 200 mm silicon wafers with either Copper or Tungsten to optimize the uniformity of removal rate with respect to polishing parameters, such as slurry flow, slurry composition, down force, relative velocity of wafer surface with pad, etc. With optimized CMP parameters for blank wafer, the WIWNU in patterned wafer were evaluated and analyzed for additional optimization in non-uniformity.

Cu CMP process development and characterization of Cu dishing with 1.8 μm Cu pad and 3.6 μm pitch in Cu/SiO2 hybrid bonding

A Cu/SiO2 hybrid bonding process was developed on 1.8 μm Cu pad size and 3.6 μm pitch. A Cu dishing profile was achieved with additional fine copper removal and barrier removal chemical mechanical planarization steps (named P2 rework and P3 rework) due to the different removal rate (RR) of Cu to SiO2. With increasing P2 rework time, the Cu dishing could be increased, because the RR of Cu was larger than that of SiO2. With increasing P3 rework time, the Cu dishing was decreased, which was due to the RR of Cu being lower than that of SiO2. The interface of Cu–Cu bonding with different Cu dishing after 350 °C annealing was studied. By choosing a proper Cu dishing value which is less than the Cu expansion in the 350 °C annealing, the daisy chain resistance per link of 1.2–1.5 Ω and 95% yield of 1000 daisy chain were achieved.

High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer

In this work, a novel stacking structure of three-layer SiGe strain relaxed buffer/strained Si0.5Ge0.5 layer for shallow trench isolation last scheme is successfully developed. Firstly, a three-layer SiGe epitaxy with Ge concentration increased from bottom to top by roughly 10% combining with each layer post growth in-situ annealing is employed to effectively constrain the threading dislocation defect in the bottom and middle strain relaxed buffer layer and the top layer of strain relaxed buffer with thickness of ∼1 μm has no obviously defect impact. Before Si0.5Ge0.5 layer epitaxy on the top of this strain relaxed buffer layer, a chemical-mechanical planarization step is employed to improve surface roughness of strain relaxed buffer layer from 6.09 nm to 0.23 nm and final Si0.5Ge0.5 layer surface roughness from 6.73 nm to 0.76 nm. Finally, on the post CMP three-layer SiGe strain relaxed buffer, a smooth and high crystal quality strained Si0.5Ge0.5 layer with a thickness of 50 nm, which is larger than its critical thickness of ∼20 nm, is successfully prepared by utilizing our new developed technique.

Advanced Process Control for Variability Control in Chemical Mechanical Polishing Process

With transistors scaling towards sub 14nm nodes, FIN-field effect transistors (FINFETs) have been the preferred design architecture to meet device requirements. The gate last/replacement metal gate (RMG) integration scheme forms the core design for FINFETs due to the advantages in thermal budgets. Chemical Mechanical Planarization (CMP) plays a key role in this integration scheme with various CMP steps supporting dummy poly gate formation, poly removal and replacement metal gate formation. And the final gate height after metal gate CMP process typically determines device resistance. Therefore, one of major requirements of metal gate CMP is to control gate height as tightly as possible for every wafer. In this paper, two fold approaches are introduced to achieve this. Integrated advanced process control (iAPC) method improves wafer to wafer variation, and zonal iAPC provides additional within wafer variation improvement. The concept of iAPC is to use data collected from each wafer and to adjust polishing time (and zone pressure for zonal iAPC case) to achieve final gate height. Using these two approaches, gate height control of less than 5nm has been demonstrated.

Advanced Process Control for Variability Control in Chemical Mechanical Polishing Process

With semiconductor technologies driving towards sub 14nm nodes, FIN based field effect transistors (FINFETs) have been the preferred design to meet device power and performance requirements. At the core of FINFET transistor design is gate last/replacement metal gate (RMG) integration scheme due to the advantages in thermal budgets. Chemical mechanical planarization has evolved from planarization technique to technology enabler for this integration scheme. Replacement metal scheme has its own share of challenges- the integration scheme is quite complex. Chemical mechanical planarization (CMP) plays a key role in enabling this integration with various CMP steps supporting dummy poly gate formation, poly removal and replacement metal gate formation. The final gate height of the replacement metal gate is one of the most important parameters controlling device resistance. Even a change of 1nm gate height can result in overall variation of 5ohms/sq resistance. This requires CMP to control gate height as tightly as possible for every wafer. The two important factors contributing to the overall gate height variation are upstream processes and the metal gate CMP process itself. It is well known that CMP has its own variability in removal rate depending on consumable life resulting in unstable gate height. The gate height variation needs to be controlled within wafer and every wafer. A dedicated metrology tool connected to the polishing tool has been employed for many years to measure wafer thickness parameters. This onboard metrology tool is used to measure every wafer and the data is used to develop automated process control to improve overall within wafer and wafer to wafer variation. A two fold approach is used to achieve this. Integrated automated process control (iAPC) is initially used to control wafer to wafer variation and furthermore, zonal integration automated process control is used to improve within wafer uniformity. The basic concept is to use metrology data collected from each wafer and create a model to adjust polishing time to achieve desired final gate height target. Using these two approaches, gate height control of less than 5nm has been demonstrated consistently. Both these approaches will be discussed in detail.

Post CMP Cleaning: a Comparison of Contact and Non-Contact Physical Cleaning Methods

Chemical mechanical planarization (CMP) process steps are increasing in frequency and criticality. The introduction of new, sensitive dielectric materials as well as sensitivity to residual slurry and particle contamination make the post CMP clean an integral part of a good yielding CMP step. Brush Scrubbing is the traditional method of post CMP cleaning. With this contact cleaning method particles are removed by direct contact of a rotating brush with the wafer surface. These particles are then swept away by the cleaning solution. This method of cleaning has some well known challenges, among them cross contamination from wafer to wafer, brush marking and scratching as well as process feedback and control. An alternative physical cleaning method utilizes the cavitation created by the presence of Megasonic energy in the process fluid to provide a non-contact method of slurry residual and particulate removal from the planarized surface. The Megasonic apparatus used in these experiments has been successfully applied to other single wafer cleaning processes and is implemented in many large volume production applications. Most mass production post CMP cleaning processes consist of a series of cleaning and chemistry steps as well as a mix of physical cleaning approaches. The challenge in quantifying effect and comparing cleaning efficiency between contact and non-contact physical cleaning has been in the isolation of cleaning results attributed to a change in method. In this work we were able to provide conditions for a direct comparison of cleaning methods in a special post CMP scrubber. This tool is configured for brush or Megasonic processes in the same chamber with the identical wafer flow from the polisher. The CMP was done on thermal SiO2 using two varieties of conventional slurry and a common pad type. Fifty wafers were split processed, half with 150835 and half with D3586. A large delta in particle removal efficiency was observed based on slurry type alone. The brush parameters were based on a long term process of record. (Table 1) Several megasonic parameters were varied to better understand the process window. Analysis of cleaning results was performed using an SP2 with a threshold of 90nm. (Figure 1) Table 1, Experimental process recipe details Brush Recipe Step Time (sec) Chemical Wafer RPM Brush RPM 1 40 NH4OH 2% 20 80 2 40 DIW 20 80 3 20 DIW 60 No Brush 4 Dry 2000 Meg Recipe 1 Step Time (sec) Chemical Wafer RPM W/cm2 1 52 NH4OH 2% 60 2.5 2 48 DIW 60 2.5 3 Dry 2000 0 Meg Recipe 2 Step Time (sec) Chemical Wafer RPM W/cm2 1 52 NH4OH 2% 60 1.85 2 48 DIW 60 1.85 3 Dry 2000 0 Meg Recipe 3 Step Time (sec) Chemical Wafer RPM W/cm2 1 90 NH4OH 2% 60 1.85 2 10 DIW 60 1.85 3 Dry 2000 0 These direct comparison tests prove that the non-contact Megasonic method equals or exceeds the cleaning results achieved with the traditional brush cleaning under identical process flow and conditions. Figure 1: Post CMP clean particle counts 90nm threshold with D3586 slurry. Figure 1

(Invited) Wafer Scale Copper Direct Plating on Thin PVD RuTa Layers: A Route to Enable Filling 30 nm Features and Below

Among all the Ru-based substrates, mixed-phase RuTa liners grown by physical vapor deposition have been explored as potential directly-platable diffusion barrier candidates. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of the applied waveform, electrical contacts and suppressor chemistry have been investigated. In order to enhance copper nucleation and wafer scale edge-to-center copper front propagation rate, a liner surface cleaning protocol is developed. The copper front propagation across the 300 mm wafer is reported as a function of the RuTa film thickness. An optimized copper direct plating process on RuTa layers as thin as 4 nm is integrated in 90 and 30 nm half pitch single and dual damascene structures. Results in terms of compatibility of the direct plated copper with the following chemical mechanical planarization step complemented with physical and electrical characterization data are reported. The direct filling of ~25 nm sacrificial fin structures is also investigated.

Wafer Scale Copper Direct Plating on Thin PVD RuTa Layers: A Route to Enable Filling 30 nm Features and Below?

Among all the Ru-based substrates, mixed-phase RuTa liners grown by physical vapor deposition have been explored as potential directly-platable diffusion barrier candidates. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of the applied waveform, electrical contacts and suppressor chemistry have been investigated. In order to enhance copper nucleation and wafer scale edge-to-center copper front propagation rate, a liner surface cleaning protocol is developed. The copper front propagation across the 300 mm wafer is reported as a function of the RuTa film thickness. An optimized copper direct plating process on RuTa layers as thin as 4 nm is integrated in 90 and 30 nm half pitch single and dual damascene structures. Results in terms of compatibility of the direct plated copper with the following chemical mechanical planarization step complemented with physical and electrical characterization data are reported. The direct filling of ∼25 nm sacrificial fin structures is also investigated.

Al CMP for Low Resistance Gate Fill for 20nm and Beyond Replacement Metal Gate

ABSTRACTAluminum (Al) gate fill has been implemented in Replacement Metal Gate (RMG) due to its low resistivity. Titanium (Ti) has been widely used as wetting layer for Al to fill the gates. For low resistance gate fill in structures with small feature size and high aspect ratio, Ti-Al metal fill becomes increasingly more challenging as we move from 20nm into 14nm FinFET and 3D type structures.Cobalt (Co) is a good wetting film for Al with better fill performance and lower resistance than Ti-Al based process. However, due to the difference in corrosion potential between Al and Co, Chemical Mechanical Planarization (CMP) creates pitting type defects on Al-Co film that increases resistance variability across pattern density. CMP induced corrosion is separated in two parts; first is the static Co corrosion happened in the acidic chemical environment in the Al slurry. Second is the galvanic corrosion from Co-Al metal boundary due to high metal electrical potential. Static corrosion can be resolved by adding a Co corrosion inhibitor in the slurry formulation1. Galvanic corrosion can be minimized by controlling Co thickness deposition and formation of complete intermetallic phase. By controlling the removal rate with respect to corrosion rate we were able to suppress corrosion significantly.We looked into compositions where the corrosion potential (Ecorr) gap between Al and Co is reduced to ≤10mV leading to reduced galvanic currents. Stabilization of the corrosion currents in both Al and Co was observed using potentiodynamic scans. The effect of pH, several oxidizers and additives on the open circuit potentials (Eoc) of Al and Co was investigated and it was found that solutions of KMnO4, saccharides and sulfonate group containing compounds help reduce the Ecorr gap in between Al and Co to ∼10 mV.Controlling the Al gate height across pattern densities and gate lengths to within few nm is another challenge for Al CMP. The industry widely used approach is to clear all Al using a slurry with high selectivity to dielectric, followed by a CMP step using a non-selective Al-to-oxide slurry. Both polishing steps need to be optimized in parallel in order to remove the incoming spacer SiN divot, minimize Al loss on gates with high pattern density or long gate length, minimize oxide loss on large open areas while maintaining low defectivity.In this paper we are presenting an innovate Al CMP process that demonstrated low gate resistance with tight distribution up to 80% pattern density. This work has been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Division Semiconductor Research & Development Center, Hopewell Junction, NY 12533.

Surface-complex films of guanidine on tantalum nitride electrochemically characterized for applications in chemical mechanical planarization

Chemical mechanical planarization (CMP) of tantalum nitride is an essential step of material processing in the fabrication of integrated circuits. This CMP step often involves the chemical formation of a structurally weak oxide-complex film on the wafer surface, followed by selective removal of the film with mechanical abrasion under reduced loading. The present work investigates certain chemical aspects of this strategy of TaN-CMP by using guanidine carbonate (GC) as a surface complexing agent, and employing electrochemical experiments. The experiments are designed to study the chemical and electrochemical origins of the CMP-specific surface complex films formed on a TaN wafer in acidic solutions of GC and hydrogen peroxide. Open circuit potential, polarization resistance, and electrochemical impedance measurements are employed to probe the surface effects that facilitate material removal in chemically prevailing CMP of TaN. The results are discussed in view of designing slurry variables to support barrier layer planarization with reduced roles of mechanical abrasion.

Chemical Mechanical Planarization Technology for Si Wafer Bonding

This paper deals with chemical mechanical planarization (CMP) technology to develop 3D (3-Dimentional) stacked Flash Memory. The purpose of IGD CMP in full wafer process is to recover local planarity and surface roughness. Based on small elastic deflection theory, the following formula is derived. CMP Step Height of local planarity H = 3.5×(W×γ/4)1/2 × { 0.75×(1-ν2)/E + 0.75×(1-ν2)/E }1/2 . When this formula is applied, local planarity H should be under 30A, which is confirmed through the experiment. Channel Silicon CMP is the important planarization process to improve the single crystal silicon property. The polished Channel Silicon layer has surface roughness of about 1A rms using colloidal silica based slurry with self stop function.

Advanced TSV Copper Electrodeposition for 3D Interconnect Applications

Robust and manufacturable processes are needed to enable a smoother and faster transfer of TSV technology from development to production. There are several steps involved with TSV technology application. Either if it is done before or after thinning the wafer, as a via first, middle or via last approach, the main steps are: via etching, lining with insulator/barrier and copper seed, deep via fill and chemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is one of thee most critical steps in forming the TSV electrodes, and copper electrodeposition process has been identified to be the most appropriate and cost effective method of filling the vias. Various critical factors with significant effect on the process performance were found: seed layer uniformity, via profile and size, stability and performance of the chemicals and equipment design. The amount and quality of the copper at the top of the vias and over the entire surface of the wafer is very important for the CMP processing. A more uniform deposition and lower overburden could significantly decrease the complexity and cost of the CMP step. The copper thickness profile between deposition and CMP can be cross-optimized to reduce dishing, increase throughput and reduce cost. This paper will focus on the deep via fill, the critical factors associated with this step and integration aspects of Cu TSV deposition step that need to be taken in consideration for successful application of this technology. A significant amount of work has been performed to develop processes that can successfully fill features of various sizes in a cost effective way. Some of the chemistries available commercially today, although have very good super-fill characteristics, have the disadvantage of forming nodular and high-stress deposits which could have a negative impact on CMP processing. An innovative process with strong bottom-up capability that significantly reduces the overburden while increasing the speed of deposition has been developed at Semitool and the characteristics of this process and advantages over previous generation processes will be presented. The effect of copper stress and copper extrusion observed during annealing step as well as approaches taken to minimize this effect will be described.

A Method for Die Thickness Reduction to sub-35 μm

AbstractSignificant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).

An efficient wet-cleaning of SiGe virtual substrates and of thick, pure Ge layers on Si(0 0 1) after a chemical mechanical planarization step

The aim of this study is to propose an efficient wet cleaning of the surfaces of the SiGe virtual substrates just after a chemical mechanical polishing step. We have first of all studied the chemical compatibility of miscellaneous solutions, such as the standard cleaning 1 (SC1), the Standard Cleaning 2 (SC2), the CARO one etc with SiGe. A definite, logarithmic-like increase of the etch rate with the Ge content has been obtained for the SC1, the SC2 and the CARO solutions (with values 1000–10,000 those of Si evidenced for pure Ge), making them unsuitable for Ge contents above 30%. We have thus investigated the efficiency of new cleaning sequences (named “DDC-SiGe” for SiGe and “HF/O 3” for pure Ge) that call upon diluted HF and ozone solutions spiked with HCl, on SiGe and pure Ge. The overall material consumption of those cleaning sequences, which increases from 10 Å for pure Si up to 130 Å for pure Ge, is quite low. The particle removal efficiency of such cleanings is around 99% for Si 0.8Ge 0.2 and Si 0.7Ge 0.3. It drops down to 83% for Si 0.5Ge 0.5 and to 65% for pure Ge. This is most probably due to pre-existing epitaxy defects which are revealed during the wet cleaning then wrongly assimilated to particles by our surface inspection tool. The metallic contaminants present on the surface after the use of our wet cleaning sequences have a surface density lower than 10 10 atoms cm −2, this whatever the Ge content of the underlying layer.

Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS

This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps.

Application of Volatility Diagrams for Low Temperature, Dry Etching, and Planarization of Copper

A thermodynamic analysis of the dry etching process for copper using halides is undertaken with the development of volatility diagrams. The construction of such diagrams for the Cu-Cl system is illustrated for temperatures ranging from 50 to 200°C. The copper condensed phase species and the partial pressures of the predominant copper vapor phase species are depicted on these diagrams as a function of the partial pressure of chlorine at various temperatures. From these diagrams, it is apparent that reactive ion etching (RIE) of copper based on a procedure previously utilized for aluminum, is inefficient at temperatures less than 200°C. However, closer examination of the metastable equilibrium line between condensed and gaseous reveals the possibility of extremely high etch rates at low temperatures, if a reducing environment based on hydrogen is utilized for etching The design of a multistep, low temperature RIE process for copper, that first requires the formation of condensed followed by the hydrogen based etching of condensed (and hence copper) due to the formation of gas, is discussed. Some important aspects for the successful implementation of this etching scheme are considered. The further utilization of this process for the purpose of reactive ion planarization of copper as a potential replacement for the problematic chemical mechanical planarization step in the damascene process, is also suggested. The role of capillarity effects in this dry planarization process is discussed briefly. © 2002 The Electrochemical Society. All rights reserved.