A Method for Die Thickness Reduction to sub-35 μm

Abstract

AbstractSignificant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).