Advanced TSV Copper Electrodeposition for 3D Interconnect Applications

Abstract

Robust and manufacturable processes are needed to enable a smoother and faster transfer of TSV technology from development to production. There are several steps involved with TSV technology application. Either if it is done before or after thinning the wafer, as a via first, middle or via last approach, the main steps are: via etching, lining with insulator/barrier and copper seed, deep via fill and chemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is one of thee most critical steps in forming the TSV electrodes, and copper electrodeposition process has been identified to be the most appropriate and cost effective method of filling the vias. Various critical factors with significant effect on the process performance were found: seed layer uniformity, via profile and size, stability and performance of the chemicals and equipment design. The amount and quality of the copper at the top of the vias and over the entire surface of the wafer is very important for the CMP processing. A more uniform deposition and lower overburden could significantly decrease the complexity and cost of the CMP step. The copper thickness profile between deposition and CMP can be cross-optimized to reduce dishing, increase throughput and reduce cost. This paper will focus on the deep via fill, the critical factors associated with this step and integration aspects of Cu TSV deposition step that need to be taken in consideration for successful application of this technology. A significant amount of work has been performed to develop processes that can successfully fill features of various sizes in a cost effective way. Some of the chemistries available commercially today, although have very good super-fill characteristics, have the disadvantage of forming nodular and high-stress deposits which could have a negative impact on CMP processing. An innovative process with strong bottom-up capability that significantly reduces the overburden while increasing the speed of deposition has been developed at Semitool and the characteristics of this process and advantages over previous generation processes will be presented. The effect of copper stress and copper extrusion observed during annealing step as well as approaches taken to minimize this effect will be described.