Charging Damage Research Articles

Surface photoconductivity of organosilicate glass dielectrics induced by vacuum-ultraviolet radiation

The temporary increase in the electrical surface conductivity of low-k organosilicate glass (SiCOH) during exposure to vacuum-ultraviolet radiation (VUV) is investigated. To measure the photoconductivity, patterned “comb structures” are deposited on dielectric films and exposed to synchrotron radiation in the range of 8–25 eV, which is in the energy range of most plasma vacuum-ultraviolet radiation. The change in photo surface conductivity induced by VUV radiation may be beneficial in limiting charging damage of dielectrics by depleting the plasma-deposited charge.

Statistical Prediction of Micro-Arcing in Radio-Frequency Plasmas for Manufacture of Semiconductor Device

A hard-arcing precursor that causes charging damage to semiconductor devices was found. The micro-arcing that occurs during the plasma etch process was statistically classified based on the optical intensity variation by using high-speed optical sensing. According to the level of effect on semiconductor device failure, the micro-arcing was categorized into soft-arcing I (8–11σ), soft-arcing II (11–15σ), and hard-arcing (over 15σ). Experimental results suggest that a sufficiently large increase in soft-arcing is directly associated with the occurrence of hard-arcing. By using this characteristic and based on a Gaussian distribution, hard-arcing was statistically predicted within 12 wafers. A mathematical model is also proposed to explain the same. This is the first control system capable of predicting and effectively restraining micro-arcing during the plasma process.

Plasma Damage Mechanism of Electron Beam Curing Process for Spin on Dielectrics

This letter presents the plasma damage mechanism of electron beam curing process for spin on dielectrics. Device damage is studied using the antenna gate metal-oxide-semiconductor field-effect transistor (MOSFET) in terms of the threshold voltage variation as a function of electron beam conditions such as ambient and cathode voltage. Threshold voltages of nMOSFET are decreased by an electron beam curing process without antenna ratio dependency. The electron energy and interlayer dielectric thickness between active devices and metal layers largely affect the variation of threshold voltage. From the experimental results, it is concluded that device damage induced by an electron beam curing process is characterized as radiation damage rather than electron charging damage. For the damage free electron beam curing process, it is essential to control the penetration depth of high-energy electrons by adjusting the cathode voltage while considering the dielectric thickness over active devices.

Multi-Beam Ion Microscopy

Over the past fifty years the scanning electron microscope (SEM) has established itself as the most versatile and productive tool for imaging and microanalysis in many areas of science and technology, and some seventy-thousand instruments generate millions of micrographs every day. Scanning electron microscopes do, however, have one fundamental limitation in that the only experimental variable available to the operator is the choice of the accelerating voltage. Although the ability to vary beam energy is both necessary and important, it is an unfortunate fact that changing the beam energy also alters many aspects of performance: imaging resolution, relative strength of different signal components, depth of beam penetration, capabilities of the various analytical systems, and the severity of charging and beam-induced damage. This makes it difficult or impossible to optimize the interaction of interest.

Hybrid simulation of a dc-enhanced radio-frequency capacitive discharge in hydrogen

A PIC-MCC/fluid hybrid model was employed to study a parallel-plate capacitively coupled radio-frequency discharge in hydrogen, under the application of a dc bias voltage. When a negative dc voltage was applied to one of the electrodes of a continuous wave (cw) plasma, a ‘beam’ of secondary electrons was formed that struck the substrate counter-electrode at nearly normal incidence. The energy distribution of the electrons striking the substrate extended all the way to VRF + |Vdc|, the sum of the peak RF voltage and the absolute value of the applied dc bias. Such directional, energetic electrons may be useful for ameliorating charging damage in etching of high aspect ratio nano-features. The vibrational distribution function of molecular hydrogen was calculated self-consistently, and was found to have a characteristic plateau for intermediate values of the vibrational quantum number, v. When a positive dc bias voltage was applied synchronously during a specified time window in the afterglow of a pulsed plasma, the ion energy distributions (IEDs) of positive ions acquired an extra peak at an energy equivalent of the applied dc voltage. The electron energy distribution function was slightly and temporarily heated during the application of the dc bias pulse. The calculated IEDs of and ions in a cw plasma without dc bias were found to be in good agreement with published experimental data.

Characterization of tunnel-oxide degradation due to plasma field oxide recess in flash memory devices

This paper presents the characterization of degradation of tunnel oxide during plasma recess of field oxide films for Shallow Trench Isolation (STI) in sub 30nm flash memory devices. Simple plasma charge damage monitor wafers with Metal-Oxide-Semiconductor (MOS) capacitor structures were used to analyze the mechanisms of degradation of tunnel oxide due to process-induced charging damage. We characterized the gate leakage currents and breakdown voltages of MOS capacitors with area antennas after performing the plasma process for field oxide recess of STI with various etching conditions in a dual-frequency capacitively coupled plasma reactor. The results showed that the degradation was strongly dependent on plasma non-uniformity, which could be improved by optimizing the radio-frequency and biasing power. Especially, we found that RF biasing power caused stress-induced leakage currents due to dielectric breakdown by the leakage current originating from the electrostatic chuck.

Method for Achieving CMOS MEMS Accelerometers with Excellent Built-in Thermal Stability and Reduced Charge Damage

ABSTRACTCapacitive CMOS MEMS sensors are usually defined by anisotropic dry etching processes (RIE and DRIE). These processes can provide clean and vertical sidewall geometry. However, during the dry-etching processes, charges are added to the gate electrodes of the on-chip MOSFET’s through metal pads and micro-structures, and the voltage may be raised to the level of breaking down the gate oxide, which leads to large leakage current and fails the circuit. On another hand, the thin spring beams in capacitive CMOS MEMS accelerometers suffer from in-plane curling and out-of-plane curling caused by stress gradient. Furthermore, the stress in the layers of MEMS structure is a function of temperature. Therefore, the in-plane curling and out-of-plane curling vary with temperature, leading to varying electrode coupling area in the sensing beams. This in turn causes variation in the sensitivity and the DC offset of sensors, meaning that usually the thermal stability of CMOS MEMS capacitive accelerometers is very poor. To cope with these problems, this work develops a new wafer-level post-CMOS process for fabricating thermally stable capacitive accelerometers. The resultant MEMS structures have high aspect ratio (e.g. 2-2.5 μm gaps versus 57 μm depth) and are insensitive to residual stress as well as temperature change. Excellent thermal stability was achieved intrinsically by making the crystalline Si layer in the sensors thick. Moreover, this process totally avoids the charge damage problem during the dry-etching procedure. For demonstration, an accelerometer sensor was fabricated by using the proposed process and was integrated with an on-chip sensing circuit in commercial 0.35 μm 2P4M CMOS process. High detection sensitivity of 595 mV/g and very low thermal variation of 1.68 mg/°C were successfully achieved.

Analytic Model of Threshold Voltage Variation Induced by Plasma Charging Damage in High-k Metal–Oxide–Semiconductor Field-Effect Transistor

We discuss plasma charging damage (PCD) to high-k gate dielectrics and the resultant threshold voltage shift (ΔVth) in n-channel metal–oxide–semiconductor field-effect transistors (n-ch MOSFETs). The PCD induced by the antenna effect is focused on, and ΔVth and its variation are estimated for MOSFETs treated by various plasma processes. We propose a ΔVth variation model based on both the power-law dependence of ΔVth on the antenna ratio r (= exposed metal interconnect area/gate area) and the r distribution deduced from an interconnect-length distribution function (ILDF) in a large-scale integrated (LSI) circuit. Then, we simulate the variations in ΔVth [σ(ΔVth)] and the subthreshold leakage current Ioff [σ(Ioff)], in accordance with the employed r distribution. The model prediction quantitatively shows the effects of PCD on σ(ΔVth) and σ(Ioff): The antenna effect is found to increase σ(ΔVth) and σ(Ioff).

Comparative Study of Plasma-Charging Damage in High-k Dielectric and p–n Junction and Their Effects on Off-State Leakage Current of Metal–Oxide–Semiconductor Field-Effect Transistors

Plasma-induced charging damage (PCD) to a metal–oxide–semiconductor field-effect transistor (MOSFET) with a high-k dielectric was studied in detail using a capacitively coupled plasma reactor for various exposure times. From the drain current versus gate voltage characteristics, we observed the threshold voltage shift (ΔVth) and the increase in reverse-leakage current (Ij) at the n+/p junction in plasma-exposed n-channel MOSFETs. The observed ΔVth in the negative direction was due to positive trap-site creation in the high-k dielectric. The combined effect by PCD increased off-state leakage current (Ioff) in n-channel MOSFETs, however, the Ij increase was found to be dominant in the Ioff increase. By employing a capacitance-measurement technique, we clarified that the Ij considerably was increased at the junction by PCD, whereas the maximum capacitance at the junction in accumulation decreased. We also identified that the generated defect site density (nd) at the junction induces the observed Ij increase as a trap-assist tunneling site.

A comprehensive study of various etch processes for the removal of silicide-block-film in submicron CMOS technologies

The removal of silicide-block-film is crucial for device stability, reliability and subsequent silicide formation. In this paper, various silicide block etch processes, i.e. dry and wet etch, were studied and compared. Possible plasma charging damage during dry etch might caused unstable PMOS threshold voltage ( V th) during H 2 annealing. The impacts of the plasma-process-induced-damage (PPID), including V th shift, its channel length dependency, and its thermal stability were investigated. The PPID can be eliminated by reducing bias power and magnetic field, while sacrificing etch rate (ER) and equipment throughput. The main advantages of wet etch are immunity from PPID, and little surface damage resulting in uniform silicide formation. However, it also has disadvantages: buffered oxide etchant (BOE) leads to the appearance of poly pinholes, and diluted hydrofluoric acid (DHF) peels the photoresist (PR) off. Therefore, wet etch can only be used in the situation of short etching time such as the combined dry and wet etch.

Measurement and simulation of spreading current in interlayer dielectric film deposition by plasma-enhanced chemical vapor deposition

A serious issue affecting metal–oxide–semiconductor field-effect transistors is plasma-induced charging damage caused by the spreading current during plasma-enhanced chemical vapor deposition of dielectric films. This current is studied in detail by direct measurement of the plasma-induced vacuum ultraviolet photocurrent through a deposited SiO2 film. The current increased with increasing antenna-wiring spacing, which spreads the electric field over a greater area. Furthermore, the photocurrent showed a parabolic dependence on film thickness. A finite element method simulation demonstrated that the current through a deposited SiO2 film increased when the spreading effect was dominant and decreased when the resistance increase was dominant.

Light Switched Plasma Charging Protection Device for High-Field Characterization and Flash Memory Protection

Plasma charging damage (PCD) is usually measured by comparing the measurement results of an undamaged reference structure to the results of structures, which intentionally received PCD. If wafer level reliability structures are required, these test structures, including the damage amplifying antenna, have to be small enough to fit into the scribeline. However, when these test structures, usually transistors, become smaller, it is harder to realize damage-free reference structures, since the ratio from pad antenna to gate area will increase. To avoid this effect, protection devices are commonly placed parallel to the gate of the reference transistors. However, most protection devices do not allow high-field measurement or the use of both polarities, which is important for in-depth PCD analysis. A device, which at the same time protects the test structure from PCD and also permits bipolar high-field stress to be applied to the test structure, is shown in this paper. Its usefulness is demonstrated on a realistic test structure and as a protection device for Flash memory cells.

A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability

Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated with a capacitive accelerometer in 0.35 µm CMOS technology. The accelerometer contains a thermally stable MEMS sensor and an on-chip CMOS sensing circuit with a chopper stabilization scheme. The temperature stabilization was achieved by forming a thick single-crystal silicon (SCS) layer at the bottom of the multi-layer MEMS structure. No leakage current due to charge damage was ever observed in the sample chips. The proposed process also led to minimal undercut of the SCS layer after MEMS structure release. The sensitivity of the accelerometer is 595 mV g−1, and the overall noise floor is 50 µg Hz−1/2 which corresponds to an effective capacitance noise floor of 0.024 aF Hz−1/2. The zero-g temperature coefficient of the accelerometer output voltage is only 1 mV °C−1 in the temperature range from 0 to 70 °C, which corresponds to an effective acceleration variation rate of 1.68 mg °C−1.

Mechanism Analysis of Plasma Charging Damage on Gate Oxide for HDP FSG Process

For its stability and relatively lower K value, FSG (fluorine silica glass) is widely used in 0.18μm and below VLSI process. In this paper, the plasma charging damage on 30Aå gate oxide from the high-density-plasma deposition (HDP) of FSG is investigated. Positive and negative nondestructive JTDDB stress is applied to fresh transistors to simulate the plasma charging current. According to the results comparison, positive plasma stress at the end of the HDP-CVD FSG deposition is found to be the major cause of damage. The damage is located near the Gate/SiO2 interface. By increasing the FSG thickness, the damage is effectively suppressed.

Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors

Threshold voltage shift (ΔVth) and its variation induced by plasma processing were investigated in detail. Two damage mechanisms occurring in an inductively coupled plasma reactor were focused on in this study; the charging damage induced by the conduction current from plasma and the physical damage attributed to the bombardment of high-energy ions. Regarding the charging damage, ΔVth was found to show a power-law dependence on antenna ratio for both SiO2 and high-k gate dielectrics in metal–oxide–semiconductor field-effect transistors (MOSFETs). The observed dependence was also confirmed from the results of a constant-current stress test, indicating that the plasma plays the role of the current source in terms of the charging damage. As for the physical damage, the recess structure in source/drain extension regions was focused on as a possible cause of ΔVth. The depth of the recess (dR) formed by the physical damage was studied using Si wafers exposed to various plasma conditions and subsequently analyzed for surface damage. The recess depth determined from the experiments and classical molecular dynamics simulations exhibits a power-law dependence on potential drop across the sheath between the plasma and the device surface (Vp-Vdc), which is used as a practical measure of the damage. On the basis of the above results, ΔVth due to the physical damage was calculated by technology computer-aided design (TCAD) device simulation for n- and p-channel MOSFETs with the recess structure. ΔVth shows a linear dependence on recess depth for both n- and p-channel MOSFETs, resulting in the power-law dependence on (Vp-Vdc) via dR. These findings provide a simple relationship among the variations of ΔVth, antenna ratio, and plasma parameters. By taking into account the findings that the MOSFET with high-k dielectrics shows a larger ΔVth due to the charging than that with SiO2, and that the MOSFETs with a smaller gate length indicate a larger ΔVth due to the Si recess structure, we can conclude that larger amount of plasma damage induces the larger ΔVth variations, i.e., the Vth variability induced by the plasma damage is difficult to suppress and will become crucial to the fabrication of future advanced devices. The proposed relationship is useful as a guideline to suppress the ΔVth variations caused by plasma damage.

Promoting of charged-device model/electrostatic discharge immunity in the dicing saw process

Abstract Polyimide (PI) dielectric as a heatproof material is commonly employed in the integrated circuit (IC) industry. In the dicing saw assembly process, de-ionized (D.I.) water which has a higher resistance is rubbed on PI material. Hence, negative electrostatic charges are generated and accumulated on gate oxide capacitor or p–n junction capacitor in each IC chip. Since the discharge path is isolated during this time, sufficient cumulated charges through some feasible electrical path will damage the IC devices in this process step. Such damaged ICs exhibit function failure. A CO2 gas flow under 2–3 kgw/cm2 gas pressure to form a weak carbonic acid in water is efficient to conduct out the accumulated charges and adequately prevent the charge damage on IC devices. The final-test yield in sub-micron analog power complementary metal–oxide–semiconductor (CMOS) ICs was impressively increased from 80% to 98%.

Multiphonon-induced charge trapping-detrapping and damage in insulators

A model is presented that interprets both electron capture (trapping) and ionization (detrapping) processes in insulators. It emphasizes the importance of the electron-phonon interactions on the electronic transitions involving defect states. These electronic transitions are accompanied by multiphonon emission or absorption in the presence of a strong electron-phonon coupling. They are governed by the Meyer-Neldel compensation rule and display a departure from Franck-Condon-like transitions. It is shown, by using earlier thermodynamic measurements [G. Moya and G. Blaise, Space Charge in Solid Dielectrics, Proceeding of the Dielectric Society Meeting (Darwin College, University of Kent, Canterbury, U.K., 1997); G. Blaise and G. Moya, 3rd International Conference on Electric Charge in Solid Insulators (unpublished)] that the entropy associated with the electron trapping and detrapping processes in oxides and polymers increases with the activation energy as predicted by the model and that the activation energies can be derived directly from such measurements. Thus, atomic or ionic movements accompanying these multiphonon electronic transitions are shown to be the cause of insulator damage and aging.

Bias frequency dependence of pn junction charging damage induced by plasma processing

Plasma-induced charging damage to pn junction in metal-oxide-semiconductor field-effect transistors (MOSFETs) was studied by using an inductively coupled plasma (ICP) reactor with Ar gas. The junction leakage current ( I leak) was measured for various source/drain to well in MOSFETs and simple diode structures. Two different rf bias frequencies, 13.56 MHz and 400 kHz, were utilized to investigate the effect of frequency on an increase in I leak. The I leak of n +/p and p +/n junctions was found to increase by a plasma treatment. In particular, more severe damage was observed for n +/p junction in both n-channel MOSFETs and the diodes. These observed results imply that plasma plays a role primarily as a positive current source. With regard to the rf bias frequency effects, samples exposed to the 400-kHz plasma were found to suffer from larger I leak than those to the 13.56 MHz. From capacitance–voltage ( C– V) measurement of junction capacitance changes, we also clarified that the observed increase in I leak was attributed to the defect density at pn junction created by the plasma charging damage.

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias are characterized in a commercial plasma etching reactor for conductor etching. The synchronous pulsed plasma characteristics are evaluated through the following: 1) Ar-based Langmuir probe diagnostics; 2) Ar/Cl2 plasma modeling utilizing the hybrid plasma equipment model and the Monte Carlo feature model for the investigation of feature profile evolutions; 3) basic etching characteristics such as average etch rate and uniformity; 4) sub-50-nm Dynamic Random Access Memory (DRAM) basic etching performance and profile control; and 5) charge damage evaluation. It is demonstrated that one can control the etching uniformity and profile in advanced gate etching, and reduce the leakage current by varying the synchronous pulsed plasma parameters. Moreover, it is shown that synchronous pulsing has the promise of significantly reducing the electron shading effects compared with source pulsing mode and continuous-wave mode. The synchronous pulsed plasma paves the way to a wider window of operating conditions, which allows new plasma etching processes to address the large number of challenges emerging in the 45-nm and below technologies.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.